Computational modeling techniques for reliability of electronic components on printed circuit boards

This paper describes modeling technology and its use in providing data governing the assembly and subsequent reliability of electronic chip components on printed circuit boards (PCBs). Products, such as mobile phones, camcorders, intelligent displays, etc., are changing at a tremendous rate where newer technologies are being applied to satisfy the demands for smaller products with increased functionality. At ever decreasing dimensions, and increasing number of input/output connections, the design of these components, in terms of dimensions and materials used, is playing a key role in determining the reliability of the final assembly. Multiphysics modeling techniques are being adopted to predict a range of interacting physics-based phenomena associated with the manufacturing process. For example, heat transfer, solidification, marangoni fluid flow, void movement, and thermal-stress. The modeling techniques used are based on finite volume methods that are conservative and take advantage of being able to represent the physical domain using an unstructured mesh. These techniques are also used to provide data on thermal induced fatigue which is then mapped into product lifetime predictions.

Polymer waveguide and VCSEL array multi-physics modelling for OECB based optical backplanes [opto-electrical circuit boards]

The deployment of OECBs (opto-electrical circuit boards) is expected to make a significant impact in the telecomm switches arena within the next five years. This will create optical backplanes with high speed point-to-point optical interconnects. The crucial aspect in the manufacturing process of the optical backplane is the successful coupling between VCSEL (vertical cavity surface emitting laser) device and embedded waveguide in the OECB. The results from a thermo-mechanical analysis are being used in a purely optical model, which solves optical energy and attenuation from the VCSEL aperture into, and then through, the waveguide. Results from the modelling are being investigated using DOE analysis to identify packaging parameters that minimise misalignment. This is achieved via a specialist optimisation software package. Results from the thermomechanical and optical models are discussed as are experimental results from the DOE.

Large scale parallel simulations for the assembly of a flip-chip component to a printed circuit

Abstract not available

Numerical modelling of solder joint formation

Solder materials are used to provide a connection between electronic components and printed circuit boards (PCBs) using either the reflow or wave soldering process. As a board assembly passes through a reflow furnace the solder (initially in the form of solder paste) melts, reflows, then solidifies, and finally deforms between the chip and board. A number of defects may occur during this process such as flux entrapment, void formation, and cracking of the joint, chip or board. These defects are a serious concern to industry, especially with trends towards increasing component miniaturisation and smaller pitch sizes. This paper presents a modelling methodology for predicting solder joint shape, solidification, and deformation (stress) during the assembly process.

A computational modelling framework to predict macroscopic phenomena in solder joint formation

A computational model of solder joint formation and the subsequent cooling behaviour is described. Given the rapid changes in the technology of printed circuit boards, there is a requirement for comprehensive models of solder joint formation which permit detailed analysis of design and optimization options. Solder joint formation is complex, involving a range of interacting phenomena. This paper describes a model implementation (as part of a more comprehensive framework) to describe the shape formation (conditioned by surface tension), heat transfer, phase change and the development of elastoviscoplastic stress. The computational modelling framework is based upon mixed finite element and finite volume procedures, and has unstructured meshes enabling arbitrarily complex geometries to be analysed. Initial results for both through-hole and surface-mount geometries are presented.

An integrated modeling approach to solder joint formation

The attachment of electronic components to printed circuit boards using solder material is a complex process. This paper presents a novel modeling methodology, which integrates the governing physics taking place. Multiphysics modeling technology, imbedded into the simulation tool—PHYSICA is used to simulate fluid flow, heat transfer, solidification, and stress evolution in an integrated manner. Results using this code are presented, detailing the mechanical response of two solder materials as they cool, solidify and then deform. The shape that a solder joint takes upon melting is predicted using the SURFACE EVOLVER code. Details are given on how these predictions can be used in the PHYSICA code to provide a modeling route by which the shape, solidification history, and resulting stress profiles can be predicted.

Material properties, geometry and their effect on the fatigue life of two flip-chip models

This paper describes how modeling technology has been used in providing fatigue life time data of two flip-chip models. Full-scale three-dimensional modeling of flip-chips under cyclic thermal loading has been combined with solder joint stand-off height prediction to analyze the stress and strain conditions in the two models. The Coffin-Manson empirical relationship is employed to predict the fatigue life times of the solder interconnects. In order to help designers in selecting the underfill material and the printed circuit board, the Young's modulus and the coefficient of thermal expansion of the underfill, as well as the thickness of the printed circuit boards are treated as variable parameters. Fatigue life times are therefore calculated over a range of these material and geometry parameters. In this paper we will also describe how the use of micro-via technology may affect fatigue life

Multiphysics modelling for electronics design

The future of many companies will depend to a large extent on their ability to initiate techniques that bring schedules, performance, tests, support, production, life-cycle-costs, reliability prediction and quality control into the earliest stages of the product creation process. Important questions for an engineer who is responsible for the quality of electronic parts such as printed circuit boards (PCBs) during design, production, assembly and after-sales support are: What is the impact of temperature? What is the impact of this temperature on the stress produced in the components? What is the electromagnetic compatibility (EMC) associated with such a design? At present, thermal, stress and EMC calculations are undertaken using different software tools that each require model build and meshing. This leads to a large investment in time, and hence cost, to undertake each of these simulations. This paper discusses the progression towards a fully integrated software environment, based on a common data model and user interface, having the capability to predict temperature, stress and EMC fields in a coupled manner. Such a modelling environment used early within the design stage of an electronic product will provide engineers with fast solutions to questions regarding thermal, stress and EMC issues. The paper concentrates on recent developments in creating such an integrated modeling environment with preliminary results from the analyses conducted. Further research into the thermal and stress related aspects of the paper is being conducted under a nationally funded project, while their application in reliability prediction will be addressed in a new European project called PROFIT.

Using computer models to identify optimal conditions for flip-chip assembly and reliability

Flip-chip assembly, developed in the early 1960s, is now being positioned as a key joining technology to achieve high-density mounting of electronic components on to printed circuit boards for high-volume, low-cost products. Computer models are now being used early within the product design stage to ensure that optimal process conditions are used. These models capture the governing physics taking place during the assembly process and they can also predict relevant defects that may occur. Describes the application of computational modelling techniques that have the ability to predict a range of interacting physical phenomena associated with the manufacturing process. For example, in the flip-chip assembly process we have solder paste deposition, solder joint shape formation, heat transfer, solidification and thermal stress. Illustrates the application of modelling technology being used as part of a larger UK study aiming to establish a process route for high-volume, low-cost, sub-100-micron pitch flip-chip assembly.

Correlation of solder paste rheology with computational simulations of the stencil printing process

Soldering technologies continue to evolve to meet the demands of the continuous miniaturisation of electronic products, particularly in the area of solder paste formulations used in the reflow soldering of surface mount devices. Stencil printing continues to be a leading process used for the deposition of solder paste onto printed circuit boards (PCBs) in the volume production of electronic assemblies, despite problems in achieving a consistent print quality at an ultra-fine pitch. In order to eliminate these defects a good understanding of the processes involved in printing is important. Computational simulations may complement experimental print trials and paste characterisation studies, and provide an extra dimension to the understanding of the process. The characteristics and flow properties of solder pastes depend primarily on their chemical and physical composition and good material property data is essential for meaningful results to be obtained by computational simulation.This paper describes paste characterisation and computational simulation studies that have been undertaken through the collaboration of the School of Aeronautical, Mechanical and Manufacturing Engineering at Salford University and the Centre for Numerical Modelling and Process Analysis at the University of Greenwich. The rheological profile of two different paste formulations (lead and lead-free) for sub 100 micron flip-chip devices are tested and applied to computational simulations of their flow behaviour during the printing process.

Impact of assembly process technologies on electronic packaging materials

Assembly processes used to bond components to printed circuit boards can have a significant impact on these boards and the final packaged component. Traditional approaches to bonding components to printed circuit boards results in heat being applied across the whole board assembly. This can lead to board warpage and possibly high residual stresses. Another approach discussed in this paper is to use Variable Frequency Microwave (VFM) heating to cure adhesives and underfills and bond components to printed circuit boards. In terms of energy considerations the use of VFM technology is much more cost effective compared to convection/radiation heating. This paper will discuss the impact of traditional reflow based processes on flexible substrates and it will demonstrate the possible advantages of using localised variable frequency microwave heating to cure materials in an electronic package.

Influence of megasonic agitation on the electrodeposition of high aspect ratio blind vias

This paper presents preliminary studies in electroplating using megasonic agitation to avoid the formation of voids within high aspect ratio microvias that are used for the redistribution of interconnects in high density interconnection technology in printed circuit boards. Through this technique, uniform deposition of metal on the side walls of the vias is possible. High frequency acoustic streaming at megasonic frequencies enables the decrease of the Nernst diffusion layer down to the sub-micron range, allowing thereby conformal electrodeposition in deep grooves. This effect enables the normally convection free liquid near the surface to be agitated. Higher throughput and better control of the material properties of the deposits can be achieved for the manufacturing of embedded interconnections and metal-based MEMS. For optimal filling performance of the microvias, a full design of experiments (DOE) and a multi-physics numerical simulation have been conducted to analyse the influence of megasonic agitation on the plating quality of the microvias. Megasonic based deposition has been found to increase the deposition rate as well as improving the quality of the metal deposits.

Modelling of the time-dependent flow behaviour of lead-free solder pastes used for flip-chip assembly applications

The market for solder paste materials in the electronic manufacturing and assembly sector is very large and consists of material and equipment suppliers and end users. These materials are used to bond electronic components (such as flip-chip, CSP and BGA) to printed circuit boards (PCB's) across a range of dimensions where the solder interconnects can be in the order of 0.05mm to 5mm in size. The non-Newtonian flow properties exhibited by solder pastes during its manufacture and printing/deposition phases have been of practical concern to surface mount engineers and researchers for many years. The printing of paste materials through very small-sized stencil apertures is known to lead to increased stencil clogging and incomplete transfer of paste to the substrate pads. At these very narrow aperture sizes the paste rheology and particle-wall interactions become crucial for consistent paste withdrawal. These non-Newtonian effects must be understood so that the new paste formulations can be optimised for consistent printing. The focus of the study reported in this paper is the characterisation of the rheological properties of solder pastes and flux mediums, and the evaluation of the effect of these properties on the pastes' printing performance at the flip-chip assembly application level. Solder pastes are known to exhibit a thixotropic behaviour, which is recognised by the decrease in apparent viscosity of paste material with time when subjected to a constant shear rate. The proper characterisation of this time-dependent theological behaviour of solder pastes is crucial for establishing the relationships between the pastes' structure and flow behaviour; and for correlating the physical parameters with paste printing performance. In this paper, we present a number of methods which have been developed for characterising the time-dependent and non-Newtonian rheological behaviour of solder pastes and flux mediums as a function of shear rates. We also present results of the study of the rheology of the solder pastes and flux mediums using the structural kinetic modelling approach, which postulates that the network structure of solder pastes breaks down irreversibly under shear, leading to time and shear dependent changes in the flow properties. Our results show that for the solder pastes used in the study, the rate and extent of thixotropy was generally found to increase with increasing shear rate. The technique demonstrated in this study has wide utility for R&D personnel involved in new paste formulation, for implementing quality control procedures used in solder paste manufacture and packaging; and for qualifying new flip-chip assembly lines

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

Modelling the performance of lead-Free solder interconnects for copper bumped flip-chip devices

Traditionally, before flip chips can be assembled the dies have to be attached with solder bumps. This process involves the deposition of metal layers on the Al pads on the dies and this is called the under bump metallurgy (UBM). In an alternative process, however, Copper (Cu) columns can be used to replace solder bumps and the UBM process may be omitted altogether. After the bumping process, the bumped dies can be assembled on to the printed circuit board (PCB) by using either solder or conductive adhesives. In this work, the reliability issues of flip chips with Cu column bumped dies have been studied. The flip chip lifetime associated with the solder fatigue failure has been modeled for a range of geometric parameters. The relative importance of these parameters is given and solder volume has been identified as the most important design parameter for long-term reliability. Another important problem that has been studied in this work is the dissolution of protection metals on the pad and Cu column in the reflow process. For small solder joints the amount of Cu which dissolves into the molten solder after the protection layers have worn out may significantly affect solder joint properties.