Modelling technology to predict flip-chip assembly

This paper describes modelling technology and its use in providing data governing the assembly of flip-chip components. Details are given on the reflow and curing stages as well as the prediction of solder joint shapes. The reflow process involves the attachment of a die to a board via solder joints. After a reflow process, underfill material is placed between the die and the substrate where it is heated and cured. Upon cooling the thermal mismatch between the die, underfill, solder bumps, and substrate will result in a nonuniform deformation profile across the assembly and hence stress. Shape predictions then thermal solidification and stress prediction are undertaken on solder joints during the reflow process. Both thermal and stress calculations are undertaken to predict phenomena occurring during the curing of the underfill material. These stresses may result in delamination between the underfill and its surrounding materials leading to a subsequent reduction in component performance and lifetime. Comparisons between simulations and experiments for die curvature will be given for the reflow and curing process

Batching decisions for assembly production systems

The two-stage assembly scheduling problem is a model for production processes that involve the assembly of final or intermediate products from basic components. In our model, there are m machines at the first stage that work in parallel, and each produces a component of a job. When all components of a job are ready, an assembly machine at the second stage completes the job by assembling the components. We study problems with the objective of minimizing the makespan, under two different types of batching that occur in some manufacturing environments. For one type, the time to process a batch on a machine is equal to the maximum of the processing times of its operations. For the other type, the batch processing time is defined as the sum of the processing times of its operations, and a setup time is required on a machine before each batch. For both models, we assume a batch availability policy, i.e., the completion times of the operations in a batch are defined to be equal to the batch completion time. We provide a fairly comprehensive complexity classification of the problems under the first type of batching, and we present a heuristic and its worst-case analysis under the second type of batching.

Using computer models to identify optimal conditions for flip-chip assembly and reliability

Flip-chip assembly, developed in the early 1960s, is now being positioned as a key joining technology to achieve high-density mounting of electronic components on to printed circuit boards for high-volume, low-cost products. Computer models are now being used early within the product design stage to ensure that optimal process conditions are used. These models capture the governing physics taking place during the assembly process and they can also predict relevant defects that may occur. Describes the application of computational modelling techniques that have the ability to predict a range of interacting physical phenomena associated with the manufacturing process. For example, in the flip-chip assembly process we have solder paste deposition, solder joint shape formation, heat transfer, solidification and thermal stress. Illustrates the application of modelling technology being used as part of a larger UK study aiming to establish a process route for high-volume, low-cost, sub-100-micron pitch flip-chip assembly.

Ultra-fine pitch flip-chip assembly using isotropic conductive adhesives

This paper discusses results from a highly interdisciplinary research project which investigated different packaging options for ultra-fine pitch, low temperature and low cost flip-chip assembly. Isotropic Conductive Adhesives (ICAs) are stencil printed to form the interconnects for the package. ICAs are utilized to ensure a low temperature assembly process of flip-chip copper column bumped packages. Results are presented on the structural integrity of novel electroformed stencils. ICA deposits at sub-100 micron pitch and the subsequent thermo-mechanical behaviour of the flip-chip ICA joints are analysed using numerical modelling techniques. Optimal design rules for enhanced performance and thermomechanical reliability of ICA assembled flip-chip packages are formulated.

A modelling and experimental analysis of the no-flow underfill process for flip-chip assembly

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfills as the application and curing of this type of underfill can be undertaken before and during the reflow process - adding high volume throughput. Adopting a no-flow underfill process may result in underfill entrapment between solder and fluid, voiding in the underfill, a possible delamination between underfill and surrounding surfaces. The magnitude of these phenomena may adversely affect the reliability of the assembly in terms of solder joint thermal fatigue. This paper presents both an experimental and mdeling analysis investigating the reliabity of a flip-chip component and how the magnitude of underfill entrapment may affect thermal-mechanical fatigue life.

Macro-micro modelling of moisture induced stresses in an ACF flip chip assembly

Purpose – This paper discusses the use of modelling techniques to predict the reliability of an anisotropic conductive film (ACF) flip chip in a humid environment. The purpose of this modelling work is to understand the role that moisture plays in the failure of ACF flip chips. Design/methodology/approach – A 3D macro-micro finite element modelling technique was used to determine the moisture diffusion and moisture-induced stresses inside the ACF flip chip. Findings – The results show that the ACF layer in the flip chip can be expected to be fully saturated with moisture after 3?h at 121°C, 100%RH, 2?atm test conditions. The swelling effect of the adhesive due to this moisture absorption causes predominately tensile stress at the interface between the adhesive and the metallization, which could cause a decrease in the contact area, and therefore an increase in the contact resistance. Originality/value – This paper introduces a macro-micro modelling technique which enables more detailed 3D modelling analysis of an ACF flip chip than previously.

Effects of thermal cycling profiles on the performance of chip-on-flex assembly using anisotropic conductive films

Anisotropic conductive films (ACFs) are widely used in the electronic packaging industries because of their fine pitch potential and the assembly process is simpler compared to the soldering process. However, there are still unsolved issues in the volume productions using ACFs. The main reason is that the effects of many factors on the interconnects are not well understood. This work focuses on the performance of ACF-bonded chip-on-flex assemblies subjected to a range of thermal cycling test conditions. Both experimental and three-dimensional finite element computer modelling methods are used. It has been revealed that greater temperature ranges and longer dwell-times give rise to higher stresses in the ACF interconnects. Higher stresses are concentrated along the edges of the chip-ACF interfaces. In the experiments, the results show that higher temperature ranges and prolonged dwell times increase contact resistance values. Close examination of the microstructures along the bond-line through the scanning electron microscope (SEM) indicates that cyclic thermal loads disjoint the conductive particles from the bump of the chip and/or pad of the substrate and this is thought to be related to the increase of the contact resistance value and the failure of the ACF joints.

Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process

This paper presents the results of a packaging process based on the stencil printing of isotropic conductive adhesives (ICAs) that form the interconnections of flip-chip bonded electronic packages. Ultra-fine pitch (sub-100-mum), low temperature (100degC), and low cost flip-chip assembly is demonstrated. The article details recent advances in electroformed stencil manufacturing that use microengineering techniques to enable stencil fabrication at apertures sizes down to 20mum and pitches as small as 30mum. The current state of the art for stencil printing of ICAs and solder paste is limited between 150-mum and 200-mum pitch. The ICAs-based interconnects considered in this article have been stencil printed successfully down to 50-mum pitch with consistent printing demonstrated at 90-mum pitch size. The structural integrity or the stencil after framing and printing is also investigated through experimentation and computational modeling. The assembly of a flip-chip package based on copper column bumped die and ICA deposits stencil printed at sub-100-mum pitch is described. Computational fluid dynamics modeling of the print performance provides an indicator on the optimum print parameters. Finally, an organic light emitting diode display chip is packaged using this assembly process

Recommendations on the nature of the passenger response time distribution to be used in the MSC 1033 assembly time analysis based on data derived from sea trials

The passenger response time distributions adopted by the International Maritime Organisation (IMO)in their assessment of the assembly time for passanger ships involves two key assumptions. The first is that the response time distribution assumes the form of a uniform random distribution and the second concerns the actual response times. These two assumptions are core to the validity of the IMO analysis but are not based on real data, being the recommendations of an IMO committee. In this paper, response time data collected from assembly trials conducted at sea on a real passanger vessel using actual passangers are presented and discussed. Unlike the IMO specified response time distributions, the data collected from these trials displays a log-normal distribution, similar to that found in land based environments. Based on this data, response time distributions for use in the IMO assesmbly for the day and night scenarios are suggested

Open ended microwave oven for flip-chip assembly

A novel open-ended waveguide cavity resonator for the microwave curing of bumps, underfills and encapsulants is described. The open oven has the potential to provide fast alignment of devices during flip-chip assembly, direct chip attach, surface mount assembly or wafer-scale level packaging. The prototype microwave oven was designed to operate at X-band for ease of testing, although a higher frequency version is planned. The device described in the paper takes the form of a waveguide cavity resonator. It is approximately square in cross-section and is filled with a low-loss dielectric with a relative permittivity of 6. It is excited by end-fed probes in order to couple power preferentially into the TM3,3,k mode with the object of forming nine 'hot-spots' in the open end. Low power tests using heat sensitive film demonstrate clearly that selective heating in multiple locations in the open end of the oven is achievable

Impact of assembly process technologies on electronic packaging materials

Assembly processes used to bond components to printed circuit boards can have a significant impact on these boards and the final packaged component. Traditional approaches to bonding components to printed circuit boards results in heat being applied across the whole board assembly. This can lead to board warpage and possibly high residual stresses. Another approach discussed in this paper is to use Variable Frequency Microwave (VFM) heating to cure adhesives and underfills and bond components to printed circuit boards. In terms of energy considerations the use of VFM technology is much more cost effective compared to convection/radiation heating. This paper will discuss the impact of traditional reflow based processes on flexible substrates and it will demonstrate the possible advantages of using localised variable frequency microwave heating to cure materials in an electronic package.

Rheological characterisation of solder pastes and isotropic conductive adhesives used for flip-chip assembly

Solder pastes and isotropic conductive adhesives (ICAs) are widely used as a principal bonding medium in the electronic industry. This study investigates the rheological behaviour of the pastes (solder paste and isotropic conductive adhesives) used for flip-chip assembly. Oscillatory stress sweep test are performed to evaluate solid characteristic and cohesiveness of the lead-free solder pastes and isotropic conductive adhesive paste materials. The results show that the G' (storage modulus) is higher than G '' (loss modulus) for the pastes material indicating a solid like behaviour. It result shows that the linear visco-elastic region for the pastes lies in a very small stress range, below 10 Pa. in addition, the stress at which the value of storage modulus is equal to that of loss modulus can be used as an indicator of the paste cohesiveness. The measured cross-over stress at G'=G '' shows that the solder paste has higher stress at G'=G '' compared to conductive adhesives. Creep-recovery test method is used to study the slump behaviour in the paste materials. The conductive adhesive paste shows a good recovery when compared to the solder pastes. (C) 2008 Elsevier B.V. All rights reserved.

Wall-slip effects in SnAgCu solder pastes used in electronics assembly applications

Solder paste is the most important strategic bonding material used in the assembly of surface mount components in electronics manufacturing. As the trend towards miniaturisation of electronic products continues, there is an increasing demand for better understanding of the flow and deformation that is, the rheological behaviour of solder paste formulations. Wall slip plays an important role in characterising the flow behaviour of solder paste materials. The problem of wall slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. In rheological measurements, slip effects can generally be avoided by using roughened surfaces for measuring geometries. In this paper, a novel technique is developed to study the effect of wall slip in the rheological measurements of lead-free solder paste. The viscosity and oscillatory data obtained for three different solder paste samples (from measuring geometries of different surface roughness) havebeen analysed and compared. In viscosity measurements, slip effects were dominant at low shear rates and the use of serrated surfaces was found to be quite effective in minimizing slip effects. Oscillatory measurements were also affected by roughening the surfaces of measuring geometries.

Modelling the time-dependent behaviour of solder pastes used in the electronics assembly applications

Solder paste is the most widely used bonding material in the assembly of surface mount devices in electronic industries. It generally has a flocculated structure (show aggregation of solder particles), and hence are known to exhibit a thixotropic behavior. This is recognized by the decrease in apparent viscosity of paste material with time when subjected to a constant shear rate. The proper characterisation of this timedependent rheological behaviour of solder pastes is crucial for establishing the relationships between the pastes’ structure and flow behaviour; and for correlating the physical parameters with paste printing performance. In this paper, we present a novel method which has been developed for characterising the timedependent and non-Newtonian rheological behaviour of solder pastes as a function of shear rates. The objective of the study reported in this paper is to investigate the thixotropic build-up behaviour of solder pastes. The stretched exponential model(SEM) has been used to model the structural changes during the build-up process and to correlate model parameters with the paste printing process.