Controlling Nanostructures for in-situ TEM Characterization

Low dimensional nanostructures, such as nanotubes and 2D sheets, have unique and promising material properties both from a fundamental science and an application standpoint. Theoretical modelling and calculations predict previously unobserved phenomena that experimental scientists often struggle to reproduce because of the difficulty in controlling and characterizing the small structures under real-world constraints. The goal of this dissertation is to controlling these structures so that nanostructures can be characterized in-situ in transmission electron microscopes (TEM) allowing for direct observation of the actual physical responses of the materials to different stimuli. Of most interest to this work are the thermal and electrical properties of carbon nanotubes, boron nitride nanotubes, and graphene. The first topic of the dissertation is using surfactants for aqueous processing to fabricate, store, and deposit the nanostructures. More specifically, thorough characterization of a new surfactant, ammonium laurate (AL), is provided and shows that this new surfactant outperforms the standard surfactant for these materials, sodium dodecyl sulfate (SDS), in almost all tested metrics. New experimental set-ups have been developed by combining specialized in-situ TEM holders with innovative device fabrication. For example, electrical characterization of graphene was performed by using an STM-TEM holder and depositing graphene from aqueous solutions onto lithographically patterned, electron transparent silicon nitride membranes. These experiments produce exciting information about the interaction between graphene and metal probes and the substrate that it rests on. Then, by adding indium to the backside of the membrane and employing the electron thermal microscopy (EThM) technique, the same type of graphene samples could be characterized for thermal transport with high spatial resolution. It is found that reduced graphene oxide sheets deposited onto a silicon nitride membrane and displaying high levels of wrinkling have higher than expected electrical and thermal conduction properties. We are clearly able to visualize the ability of graphene to spread heat away from an electronic hot spot and into the substrate.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.