Occurrence of OsHV-1 in Crassostrea gigas cultured in Ireland during an exceptionally warm summer. Selection of less susceptible oysters

The occurrence of OsHV-1, a herpes virus causing mass mortality in the Pacific oyster Crassostrea gigas was investigated with the aim to select individuals with different susceptibility to the infection. Naïve spat transferred to infected areas and juveniles currently being grown at those sites were analyzed using molecular and histology approaches. The survey period distinguishes itself by very warm temperatures reaching up to 3.5°C above the average. The virus was not detected in the virus free area although a spread of the disease could be expected due to high temperatures. Overall mortality, prevalence of infection and viral load was higher in spat confirming the higher susceptibility in early life stages. OsHV-1 and oyster mortality were detected in naïve spat after 15 days of cohabitation with infected animals. Although, infection was associated with mortality in spat, the high seawater temperatures could also be the direct cause of mortality at the warmest site. One stock of juveniles suffered an event of abnormal mortality that was significantly associated with OsHV-1 infection. Those animals were infected with a previously undescribed microvariant whereas the other stocks were infected with OsHV-1 μVar. Cell lesions due to the infection were observed by histology and true infections were corroborated by in situ hybridization. Survivors from the natural outbreak were exposed to OsHV-1 μVar by intramuscular injection and were compared to naïve animals. The survival rate in previously exposed animals was significantly higher than in naïve oysters. Results derived from this study allowed the selection of animals that might possess interesting characteristics for future analysis on OsHV-1 resistance.

Dr. Richard Caulfield: antiquarian, scholar and academic librarian

The history of higher learning in Cork can be traced from its late eighteenth-century origins to its present standing within the extended confines of the Neo-Gothic architecture of University College, Cork. This institution, founded in 1845 was the successor and ultimate achievement of its forerunner, the Royal Cork Institution. The opening in 1849 of the college, then known as Queen's College, Cork, brought about a change in the role of the Royal Cork Institution as a centre of education. Its ambition of being the 'Munster College' was subsumed by the Queen's College even though it continued to function as a centre of learning up to the 1805. At this time its co-habitant, the School of Design, received a new wing under the benevolent patronage of William Crawford, and the Royal Cork Institution ceased to exist as the centre for cultural, technical and scientific learning it had set out to be. The building it occupied is today known as the Crawford Municipal Art Gallery.

Engaging with leadership development in Irish academic libraries: some reflections of the Future Leaders Programme (FLP)

Four librarians from Irish university libraries completed the U.K. Future Leaders Programme (FLP) in 2010. In this article they recount their experience and assess the effect of the programme on their professional practice and the value for their institutions. The programme is explored in the context of the Irish higher education environment, which is facing significant challenges due to the demise of the Celtic Tiger economy. A brief review of the literature relating to structured programmes to prepare librarians for senior positions, is presented. The structure and content of the FLP and the learning methodologies, theories, tools and techniques used throughout are discussed. The article suggests that the programme has real value for both individuals and institutions and that it can play a significant role in succession planning and the leadership development of librarians

Systematic delay-driven power optimisation and power-driven delay optimisation of combinational circuits

With the proliferation of mobile wireless communication and embedded systems, the energy efficiency becomes a major design constraint. The dissipated energy is often referred as the product of power dissipation and the input-output delay. Most of electronic design automation techniques focus on optimising only one of these parameters either power or delay. Industry standard design flows integrate systematic methods of optimising either area or timing while for power consumption optimisation one often employs heuristics which are characteristic to a specific design. In this work we answer three questions in our quest to provide a systematic approach to joint power and delay Optimisation. The first question of our research is: How to build a design flow which incorporates academic and industry standard design flows for power optimisation? To address this question, we use a reference design flow provided by Synopsys and integrate in this flow academic tools and methodologies. The proposed design flow is used as a platform for analysing some novel algorithms and methodologies for optimisation in the context of digital circuits. The second question we answer is: Is possible to apply a systematic approach for power optimisation in the context of combinational digital circuits? The starting point is a selection of a suitable data structure which can easily incorporate information about delay, power, area and which then allows optimisation algorithms to be applied. In particular we address the implications of a systematic power optimisation methodologies and the potential degradation of other (often conflicting) parameters such as area or the delay of implementation. Finally, the third question which this thesis attempts to answer is: Is there a systematic approach for multi-objective optimisation of delay and power? A delay-driven power and power-driven delay optimisation is proposed in order to have balanced delay and power values. This implies that each power optimisation step is not only constrained by the decrease in power but also the increase in delay. Similarly, each delay optimisation step is not only governed with the decrease in delay but also the increase in power. The goal is to obtain multi-objective optimisation of digital circuits where the two conflicting objectives are power and delay. The logic synthesis and optimisation methodology is based on AND-Inverter Graphs (AIGs) which represent the functionality of the circuit. The switching activities and arrival times of circuit nodes are annotated onto an AND-Inverter Graph under the zero and a non-zero-delay model. We introduce then several reordering rules which are applied on the AIG nodes to minimise switching power or longest path delay of the circuit at the pre-technology mapping level. The academic Electronic Design Automation (EDA) tool ABC is used for the manipulation of AND-Inverter Graphs. We have implemented various combinatorial optimisation algorithms often used in Electronic Design Automation such as Simulated Annealing and Uniform Cost Search Algorithm. Simulated Annealing (SMA) is a probabilistic meta heuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. We used SMA to probabilistically decide between moving from one optimised solution to another such that the dynamic power is optimised under given delay constraints and the delay is optimised under given power constraints. A good approximation to the global optimum solution of energy constraint is obtained. Uniform Cost Search (UCS) is a tree search algorithm used for traversing or searching a weighted tree, tree structure, or graph. We have used Uniform Cost Search Algorithm to search within the AIG network, a specific AIG node order for the reordering rules application. After the reordering rules application, the AIG network is mapped to an AIG netlist using specific library cells. Our approach combines network re-structuring, AIG nodes reordering, dynamic power and longest path delay estimation and optimisation and finally technology mapping to an AIG netlist. A set of MCNC Benchmark circuits and large combinational circuits up to 100,000 gates have been used to validate our methodology. Comparisons for power and delay optimisation are made with the best synthesis scripts used in ABC. Reduction of 23% in power and 15% in delay with minimal overhead is achieved, compared to the best known ABC results. Also, our approach is also implemented on a number of processors with combinational and sequential components and significant savings are achieved.

Innovation and evolution: challenges and opportunities for 21st century academic and research libraries

A report from the inaugural CONUL (Consortium of National & University Libraries) conference held in the Radisson Blu Hotel, Athlone, June 3rd & 4th 2015.