2 resultados para Somatotropic axis

em CORA - Cork Open Research Archive - University College Cork - Ireland


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The deposition by atomic vapor deposition of highly c-axis-oriented Aurivillius phase Bi 5Ti 3FeO 15 (BTFO) thin films on (100) Si substrates is reported. Partially crystallized BTFO films with c-axis perpendicular to the substrate surface were first deposited at 610°C (8 excess Bi), and subsequently annealed at 820°C to get stoichiometric composition. After annealing, the films were highly c-axis-oriented, showing only (00l) peaks in x-ray diffraction (XRD), up to (0024). Transmission electron microscopy (TEM) confirms the BTFO film has a clear layered structure, and the bismuth oxide layer interleaves the four-block pseudoperovskite layer, indicating the n 4 Aurivillius phase structure. Piezoresponse force microscopy measurements indicate strong in-plane piezoelectric response, consistent with the c-axis layered structure, shown by XRD and TEM.

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Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications.