Engineering design of an integrated sustainable process system for cassava biobased materials

Cassava contributes significantly to biobased material development. Conventional approaches for its bio-derivative-production and application cause significant wastes, tailored material development challenges, with negative environmental impact and application limitations. Transforming cassava into sustainable value-added resources requires redesigning new approaches. Harnessing unexplored material source, and downstream process innovations can mitigate challenges. The ultimate goal proposed an integrated sustainable process system for cassava biomaterial development and potential application. An improved simultaneous release recovery cyanogenesis (SRRC) methodology, incorporating intact bitter cassava, was developed and standardized. Films were formulated, characterised, their mass transport behaviour, simulating real-distribution-chain conditions quantified, and optimised for desirable properties. Integrated process design system, for sustainable waste-elimination and biomaterial development, was developed. Films and bioderivatives for desired MAP, fast-delivery nutraceutical excipients and antifungal active coating applications were demonstrated. SRRC-processed intact bitter cassava produced significantly higher yield safe bio-derivatives than peeled, guaranteeing 16% waste-elimination. Process standardization transformed entire root into higher yield and clarified colour bio-derivatives and efficient material balance at optimal global desirability. Solvent mass through temperature-humidity-stressed films induced structural changes, and influenced water vapour and oxygen permeability. Sevenunit integrated-process design led to cost-effectiveness, energy-efficient and green cassava processing and biomaterials with zero-environment footprints. Desirable optimised bio-derivatives and films demonstrated application in desirable in-package O2/CO2, mouldgrowth inhibition, faster tablet excipient nutraceutical dissolutions and releases, and thymolencapsulated smooth antifungal coatings. Novel material resources, non-root peeling, zero-waste-elimination, and desirable standardised methodology present promising process integration tools for sustainable cassava biobased system development. Emerging design outcomes have potential applications to mitigate cyanide challenges and provide bio-derivative development pathways. Process system leads to zero-waste, with potential to reshape current style one-way processes into circular designs modelled on nature's effective approaches. Indigenous cassava components as natural material reinforcements, and SRRC processing approach has initiated a process with potential wider deployment in broad product research development. This research contributes to scientific knowledge in material science and engineering process design.

Exploration of the relationship between tacit knowledge and software system test complexity

This research has explored the relationship between system test complexity and tacit knowledge. It is proposed as part of this thesis, that the process of system testing (comprising of test planning, test development, test execution, test fault analysis, test measurement, and case management), is directly affected by both complexity associated with the system under test, and also by other sources of complexity, independent of the system under test, but related to the wider process of system testing. While a certain amount of knowledge related to the system under test is inherent, tacit in nature, and therefore difficult to make explicit, it has been found that a significant amount of knowledge relating to these other sources of complexity, can indeed be made explicit. While the importance of explicit knowledge has been reinforced by this research, there has been a lack of evidence to suggest that the availability of tacit knowledge to a test team is of any less importance to the process of system testing, when operating in a traditional software development environment. The sentiment was commonly expressed by participants, that even though a considerable amount of explicit knowledge relating to the system is freely available, that a good deal of knowledge relating to the system under test, which is demanded for effective system testing, is actually tacit in nature (approximately 60% of participants operating in a traditional development environment, and 60% of participants operating in an agile development environment, expressed similar sentiments). To cater for the availability of tacit knowledge relating to the system under test, and indeed, both explicit and tacit knowledge required by system testing in general, an appropriate knowledge management structure needs to be in place. This would appear to be required, irrespective of the employed development methodology.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.

Hardware processors for pairing-based cryptography

Bilinear pairings can be used to construct cryptographic systems with very desirable properties. A pairing performs a mapping on members of groups on elliptic and genus 2 hyperelliptic curves to an extension of the finite field on which the curves are defined. The finite fields must, however, be large to ensure adequate security. The complicated group structure of the curves and the expensive field operations result in time consuming computations that are an impediment to the practicality of pairing-based systems. The Tate pairing can be computed efficiently using the ɳT method. Hardware architectures can be used to accelerate the required operations by exploiting the parallelism inherent to the algorithmic and finite field calculations. The Tate pairing can be performed on elliptic curves of characteristic 2 and 3 and on genus 2 hyperelliptic curves of characteristic 2. Curve selection is dependent on several factors including desired computational speed, the area constraints of the target device and the required security level. In this thesis, custom hardware processors for the acceleration of the Tate pairing are presented and implemented on an FPGA. The underlying hardware architectures are designed with care to exploit available parallelism while ensuring resource efficiency. The characteristic 2 elliptic curve processor contains novel units that return a pairing result in a very low number of clock cycles. Despite the more complicated computational algorithm, the speed of the genus 2 processor is comparable. Pairing computation on each of these curves can be appealing in applications with various attributes. A flexible processor that can perform pairing computation on elliptic curves of characteristic 2 and 3 has also been designed. An integrated hardware/software design and verification environment has been developed. This system automates the procedures required for robust processor creation and enables the rapid provision of solutions for a wide range of cryptographic applications.

Energy harvesting for monitoring bridges over their operational life

The use of energy harvesting materials for large infrastructure is a promising and growing field. In this regard, the use of such harvesters for the purpose of structural health monitoring of bridges has been proposed in recent times as one of the feasible options since the deployment of them can remove the necessity of an external power source. This paper addresses the performance issue of such monitors over the life-cycle of a bridge as it deteriorates and the live load on the structure increases. In this regard, a Lead Zirconate Titanate (PZT) material is considered as the energy harvesting material and a comparison is carried out over the operational life of a reinforced concrete bridge. The evolution of annual average daily traffic (AADT) is taken into consideration, as is the degradation of the structure over time, due to the effects of corrosion. Evolution of such harvested energy is estimated over the life-cycle of the bridge and the sensitivity of harvested energy is investigated for varying rates of degradation and changes in AADT. The study allows for designing and understanding the potential of energy harvesters as a health monitor for bridges. This paper also illustrates how the natural growth of traffic on a bridge over time can accentuate the identification of damage, which is desirable for an ageing structure. The paper also assesses the impact and effects of deployment of harvesters in a bridge as a part of its design process, considering performance over the entire life-cycle versus a deployment at a certain age of the structure.