5 resultados para Lateral bipolar junction transistors
em CORA - Cork Open Research Archive - University College Cork - Ireland
Resumo:
A novel Lorenz-type system of nonlinear differential equations is proposed. Unlike the original Lorenz system, where the chaotic dynamics remain confined to the positive half-space with respect to the Z state variable due to a limiting threshold effect, the proposed system enables bipolar swing of this state variable. In addition, the classical set of parameters (a, b, c) controlling the behavior of the Lorenz system are reduced to a single parameter, namely a. Two possible modes of operation are admitted by the system; switching between these two modes results in the creation of a complex butterfly chaotic attractor. Numerical simulations and results from an experimental setup are presented
Resumo:
This work performs an extensive charterisation of precision targeted throwing in professional and recreational darts. The goal is to identify the contributing factors for lateral drift or throwing inaccuracy in the horizontal plane. A multitechnology approach is adopted whereby a custom built body area network of wireless inertial measurement devices monitor tilt, force and timing, an optical 3D motion capture system provides a complete kinematic model of the subject, electromyography sensors monitor muscle activation patterns and a force plate and pressure mat capture tactile pressure and force measurements. The study introduces the concept of constant throwing rhythm and highlights how landing errors in the horizontal plane can be attributable to a number of variations in arm force and speed, centre of gravity and the movements of some of the bodies non throw related extremities.
Resumo:
Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.
Resumo:
The work in this thesis concerns the advanced development of polymeric membranes of two types; pervaporation and lateral-flow. The former produced from a solution casting method and the latter from a phase separation. All membranes were produced from casting lacquers. Early research centred on the development of viable membranes. This led to a supported polymer blend pervaporation membrane. Selective layer: plasticized 4:1 mass ratio sodium-alginate: poly(vinyl-alcohol) polymer blend. Using this membrane, pervaporation separation of ethanol/water mixtures was carefully monitored as a function of film thickness and time. Contrary to literature expectations, these films showed increased selectivity and decreased flux as film thickness was reduced. It is argued that morphology and structure of the polymer blend changes with thickness and that these changes define membrane efficiency. Mixed matrix membrane development was done using spherical, discreet, size-monodisperse mesoporous silica particles of 1.8 - 2μm diameter, with pore diameters of ~1.8 nm were incorporated into a poly(vinyl alcohol) [PVA] matrix. Inclusion of silica benefitted pervaporation performance for the dehydration of ethanol, improving flux and selectivity throughout in all but the highest silica content samples. Early lateral-flow membrane research produced a membrane from a basic lacquer composition required for phase inversion; polymer, solvent and non-solvent. Results showed that bringing lacquers to cloud point benefits both the pore structure and skin layers of the membranes. Advancement of this work showed that incorporation of ethanol as a mesosolvent into the lacquer effectively enhances membrane pore structure resulting in an improvement in lateral flow rates of the final membranes. This project details the formation mechanics of pervaporation and lateral-flow membranes and how these can be controlled. The principle methods of control can be applied to the formation of any other flat sheet polymer membranes, opening many avenues of future membrane research and industrial application.
Resumo:
In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.