A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Synthesis & characterisation of group IV semiconducting nanowires

Semiconductor nanowires, particularly group 14 semiconductor nanowires, have been the subject of intensive research in the recent past. They have been demonstrated to provide an effective, versatile route towards the continued miniaturisation and improvement of microelectronics. This thesis aims to highlight some novel ways of fabricating and controlling various aspects of the growth of Si and Ge nanowires. Chapter 1 highlights the primary technique used for the growth of nanowires in this study, namely, supercritical fluid (SCF) growth reactions. The advantages (and disadvantages) of this technique for the growth of Si and Ge nanowires are highlighted, citing numerous examples from the past ten years. The many variables involved in this technique are discussed along with the resultant characteristics of nanowires produced (diameter, doping, orientation etc.). Chapter 2 outlines the experimental methodologies used in this thesis. The analytical techniques used for the structural characterisation of nanowires produced are also described as well as the techniques used for the chemical analysis of various surface terminations. Chapter 3 describes the controlled self-seeded growth of highly crystalline Ge nanowires, in the absence of conventional metal seed catalysts, using a variety of oligosilylgermane precursors and mixtures of germane and silane compounds. A model is presented which describes the main stages of self-seeded Ge nanowire growth (nucleation, coalescence and Ostwald ripening) from the oligosilylgermane precursors and in conjunction with TEM analysis, a mechanism of growth is proposed. Chapter 4 introduces the metal assisted etching (MAE) of Si substrates to produce Si nanowires. A single step metal-assisted etch (MAE) process, utilising metal ion-containing HF solutions in the absence of an external oxidant, was developed to generate heterostructured Si nanowires with controllable porous (isotropically etched) and non-porous (anisotropically etched) segments. In Chapter 5 the bottom-up growth of Ge nanowires, similar to that described in Chapter 3, and the top down etching of Si, described in Chapter 4, are combined. The introduction of a MAE processing step in order to “sink” the Ag seeds into the growth substrate, prior to nanowire growth, is shown to dramatically decrease the mean nanowire diameters and to narrow the diameter distributions. Finally, in Chapter 6, the biotin – streptavidin interaction was explored for the purposes of developing a novel Si junctionless nanowire transistor (JNT) sensor.

Investigation of numerical atomic orbitals for first-principles calculations of the electronic and transport properties of silicon nanowire structures

This thesis is focused on the application of numerical atomic basis sets in studies of the structural, electronic and transport properties of silicon nanowire structures from first-principles within the framework of Density Functional Theory. First we critically examine the applied methodology and then offer predictions regarding the transport properties and realisation of silicon nanowire devices. The performance of numerical atomic orbitals is benchmarked against calculations performed with plane waves basis sets. After establishing the convergence of total energy and electronic structure calculations with increasing basis size we have shown that their quality greatly improves with the optimisation of the contraction for a fixed basis size. The double zeta polarised basis offers a reasonable approximation to study structural and electronic properties and transferability exists between various nanowire structures. This is most important to reduce the computational cost. The impact of basis sets on transport properties in silicon nanowires with oxygen and dopant impurities have also been studied. It is found that whilst transmission features quantitatively converge with increasing contraction there is a weaker dependence on basis set for the mean free path; the double zeta polarised basis offers a good compromise whereas the single zeta basis set yields qualitatively reasonable results. Studying the transport properties of nanowire-based transistor setups with p+-n-p+ and p+-i-p+ doping profiles it is shown that charge self-consistency affects the I-V characteristics more significantly than the basis set choice. It is predicted that such ultrascaled (3 nm length) transistors would show degraded performance due to relatively high source-drain tunnelling currents. Finally, it is shown the hole mobility of Si nanowires nominally doped with boron decreases monotonically with decreasing width at fixed doping density and increasing dopant concentration. Significant mobility variations are identified which can explain experimental observations.

Development of inversion-mode and junctionless Indium-Gallium-Arsenide MOSFETs

This PhD covers the development of planar inversion-mode and junctionless Al2O3/In0.53Ga0.47As metal-oxidesemiconductor field-effect transistors (MOSFETs). An implant activation anneal was developed for the formation of the source and drain (S/D) of the inversionmode MOSFET. Fabricated inversion-mode devices were used as test vehicles to investigate the impact of forming gas annealing (FGA) on device performance. Following FGA, the devices exhibited a subthreshold swing (SS) of 150mV/dec., an ION/IOFF of 104 and the transconductance, drive current and peak effective mobility increased by 29%, 25% and 15%, respectively. An alternative technique, based on the fitting of the measured full-gate capacitance vs gate voltage using a selfconsistent Poisson-Schrödinger solver, was developed to extract the trap energy profile across the full In0.53Ga0.47As bandgap and beyond. A multi-frequency inversion-charge pumping approach was proposed to (1) study the traps located at energy levels aligned with the In0.53Ga0.47As conduction band and (2) separate the trapped charge and mobile charge contributions. The analysis revealed an effective mobility (μeff) peaking at ~2850cm2/V.s for an inversion-charge density (Ninv) = 7*1011cm2 and rapidly decreasing to ~600cm2/V.s for Ninv = 1*1013 cm2, consistent with a μeff limited by surface roughness scattering. Atomic force microscopy measurements confirmed a large surface roughness of 1.95±0.28nm on the In0.53Ga0.47As channel caused by the S/D activation anneal. In order to circumvent the issue relative to S/D formation, a junctionless In0.53Ga0.47As device was developed. A digital etch was used to thin the In0.53Ga0.47As channel and investigate the impact of channel thickness (tInGaAs) on device performance. Scaling of the SS with tInGaAs was observed for tInGaAs going from 24 to 16nm, yielding a SS of 115mV/dec. for tInGaAs = 16nm. Flat-band μeff values of 2130 and 1975cm2/V.s were extracted on devices with tInGaAs of 24 and 20nm, respectively

Semiconductor nanowire fabrication via bottom-up & top-down paradigms

Semiconductor nanowires are pseudo 1-D structures where the magnitude of the semiconducting material is confined to a length of less than 100 nm in two dimensions. Semiconductor nanowires have a vast range of potential applications, including electronic (logic devices, diodes), photonic (laser, photodetector), biological (sensors, drug delivery), energy (batteries, solar cells, thermoelectric generators), and magnetic (spintronic, memory) devices. Semiconductor nanowires can be fabricated by a range of methods which can be categorised into one of two paradigms, bottom-up or top-down. Bottom-up processes can be defined as those where structures are assembled from their sub-components in an additive fashion. Top-down fabrication strategies use sculpting or etching to carve structures from a larger piece of material in a subtractive fashion. This seminar will detail a number of novel routes to fabricate semiconductor nanowires by both bottom-up and top-down paradigms. Firstly, a novel bottom-up route to fabricate Ge nanowires with controlled diameter distributions in the sub-20 nm regime will be described. This route details nanowire synthesis and diameter control in the absence of a foreign seed metal catalyst. Additionally a top-down route to nanowire array fabrication will be detailed outlining the importance of surface chemistry in high-resolution electron beam lithography (EBL) using hydrogen silsesquioxane (HSQ) on Ge and Bi2Se3 surfaces. Finally, a process will be described for the directed self-assembly of a diblock copolymer (PS-b-PDMS) using an EBL defined template. This section will also detail a route toward selective template sidewall wetting of either block in the PS-b-PDMS system, through tailored functionalisation of the template and substrate surfaces.

Au nanorods-semiconductor nanowire hybrid nanostructures : nanofabrication techniques and optoelectronic properties

The objective of this thesis is the exploration and characterization of novel Au nanorod-semiconductor nanowire hybrid nanostructures. I provide a comprehensive bottom-up approach in which, starting from the synthesis and theoretical investigation of the optical properties of Au nanorods, I design, nanofabricate and characterize Au nanorods-semiconductor nanowire hybrid nanodevices with novel optoelectronic capabilities compared to the non-hybrid counterpart. In this regards, I first discuss the seed-mediated protocols to synthesize Au nanorods with different sizes and the influence of nanorod geometries and non-homogeneous surrounding medium on the optical properties investigated by theoretical simulation. Novel methodologies for assembling Au nanorods on (i) a Si/SiO2 substrate with highly-ordered architecture and (ii) on semiconductor nanowires with spatial precision are developed and optimized. By exploiting these approaches, I demonstrate that Raman active modes of an individual ZnO nanowire can be detected in non-resonant conditions by exploring the longitudinal plasmonic resonance mediation of chemical-synthesized Au nanorods deposited on the nanowire surface otherwise not observable on bare ZnO nanowire. Finally, nanofabrication and detailed electrical characterization of ZnO nanowire field-effect transistor (FET) and optoelectronic properties of Au nanorods - ZnO nanowire FET tunable near-infrared photodetector are investigated. In particular we demonstrated orders of magnitude enhancement in the photocurrent intensity in the explored range of wavelengths and 40 times faster time response compared to the bare ZnO FET detector. The improved performance, attributed to the plasmonicmediated hot-electron generation and injection mechanism underlying the photoresponse is investigated both experimentally and theoretically. The miniaturized, tunable and integrated capabilities offered by metal nanorodssemicondictor nanowire device architectures presented in this thesis work could have an important impact in many application fields such as opto-electronic sensors, photodetectors and photovoltaic devices and open new avenues for designing of novel nanoscale optoelectronic devices.

Nanosize effect in germanium nanowire growth with binary metal alloys

This article describes feasible and improved ways towards enhanced nanowire growth kinetics by reducing the equilibrium solute concentration in the liquid collector phase in a vapor-liquid-solid (VLS) like growth model. Use of bi-metallic alloy seeds (AuxAg1-x) influences the germanium supersaturation for a faster nucleation and growth kinetics. Nanowire growth with ternary eutectic alloys shows Gibbs-Thompson effect with diameter dependent growth rate. In-situ transmission electron microscopy (TEM) annealing experiments directly confirms the role of equilibrium concentration in nanowire growth kinetics and was used to correlate the equilibrium content of metastable alloys with the growth kinetics of Ge nanowires. The shape and geometry of the heterogeneous interfaces between the liquid eutectic and solid Ge nanowires were found to vary as a function of nanowire diameter and eutectic alloy composition.

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications.

Modifying the band gap and optical properties of Germanium nanowires by surface termination

Semiconductor nanowires, based on silicon (Si) or germanium (Ge) are leading candidates for many ICT applications, including next generation transistors, optoelectronics, gas and biosensing and photovoltaics. Key to these applications is the possibility to tune the band gap by changing the diameter of the nanowire. Ge nanowires of different diameter have been studied with H termination, but, using ideas from chemistry, changing the surface terminating group can be used to modulate the band gap. In this paper we apply the generalised gradient approximation of density functional theory (GGA-DFT) and hybrid DFT to study the effect of diameter and surface termination using –H, –NH2 and –OH groups on the band gap of (001), (110) and (111) oriented germanium nanowires. We show that the surface terminating group allows both the magnitude and the nature of the band gap to be changed. We further show that the absorption edge shifts to longer wavelength with the –NH2 and –OH terminations compared to the –H termination and we trace the origin of this effect to valence band modifications upon modifying the nanowire with –NH2 or –OH. These results show that it is possible to tune the band gap of small diameter Ge nanowires over a range of ca. 1.1 eV by simple surface chemistry.

Creation of a complex butterfly attractor using a novel Lorenz-type system

A novel Lorenz-type system of nonlinear differential equations is proposed. Unlike the original Lorenz system, where the chaotic dynamics remain confined to the positive half-space with respect to the Z state variable due to a limiting threshold effect, the proposed system enables bipolar swing of this state variable. In addition, the classical set of parameters (a, b, c) controlling the behavior of the Lorenz system are reduced to a single parameter, namely a. Two possible modes of operation are admitted by the system; switching between these two modes results in the creation of a complex butterfly chaotic attractor. Numerical simulations and results from an experimental setup are presented

Nanostructured ferroelectric materials

Nanostructured materials are central to the evolution of future electronics and information technologies. Ferroelectrics have already been established as a dominant branch in the electronics sector because of their diverse application range such as ferroelectric memories, ferroelectric tunnel junctions, etc. The on-going dimensional downscaling of materials to allow packing of increased numbers of components onto integrated circuits provides the momentum for the evolution of nanostructured ferroelectric materials and devices. Nanoscaling of ferroelectric materials can result in a modification of their functionality, such as phase transition temperature or Curie temperature (TC), domain dynamics, dielectric constant, coercive field, spontaneous polarisation and piezoelectric response. Furthermore, nanoscaling can be used to form high density arrays of monodomain ferroelectric nanostructures, which is desirable for the miniaturisation of memory devices. This thesis details the use of various types of nanostructuring approaches to fabricate arrays of ferroelectric nanostructures, particularly non-oxide based systems. The introductory chapter reviews some exemplary research breakthroughs in the synthesis, characterisation and applications of nanoscale ferroelectric materials over the last decade, with priority given to novel synthetic strategies. Chapter 2 provides an overview of the experimental methods and characterisation tools used to produce and probe the properties of nanostructured antimony sulphide (Sb2S3), antimony sulpho iodide (SbSI) and lead titanate zirconate (PZT). In particular, Chapter 2 details the general principles of piezoresponse microscopy (PFM). Chapter 3 highlights the fabrication of arrays of Sb2S3 nanowires with variable diameters using newly developed solventless template-based approach. A detailed account of domain imaging and polarisation switching of these nanowire arrays is also provided. Chapter 4 details the preparation of vertically aligned arrays of SbSI nanorods and nanowires using a surface-roughness assisted vapour-phase deposition method. The qualitative and quantitative nanoscale ferroelectric properties of these nanostructures are also discussed. Chapter 5 highlights the fabrication of highly ordered arrays of PZT nanodots using block copolymer self-assembled templates and their ferroelectric characterisation using PFM. Chapter 6 summarises the conclusions drawn from the results reported in chapters 3, 4 and 5 and the future work.

Block copolymer self-assembly based device structures

This thesis investigated the block copolymer (BCP) thin film characteristics and pattern formation using a set of predetermined molecular weights of PS-b-PMMA and PS-b-PDMS. Post BCP pattern fabrication on the required base substrate a dry plasma etch process was utilised for successful pattern transfer of the BCP resist onto underlying substrate. The resultant sub-10 nm device features were used in front end of line (FEoL) fabrication of active device components in integrated circuits (IC). The potential use of BCP templates were further extended to metal and metal-oxide nanowire fabrication. These nanowires were further investigated in real-time applications as novel sensors and supercapacitors.

Carbon nanotubes as materials in nanotechnology

Carbon nanotubes (CNTs) are hollow tubes of sp2-hybridised carbon with diameters of the order of nanometres. Due to their unique physical properties, which include ballistic transport and high mechanical strength, they are of significant interest for technological applications. The electronic properties of CNTs are of particular interest for use as gas sensors, interconnect materials in the semi-conductor industry and as the channel material in CNT based field effect transistors. The primary difficulty associated with the use of CNTs in electronic applications is the inability to control electronic properties at the growth stage; as grown CNTs consist of a mixture of metallic and semi-conducting CNTs. Doping has the potential to solve this problem and is a focus of this thesis. Nitrogen-doped CNTs typically have defective structures; the usual hollow CNT structure is replaced by a series of compartments. Through density functional theory (DFT) calculations and experimental results, we propose an explanation for the defective structures obtained, based on the stronger binding of N to the growth catalyst in comparison to C. In real electronic devices, CNTs need to be contacted to metal, we generate the current-voltage (IV) characteristics of metal-contacted CNTs considering both the effect of dopants and the structure of the interface region on electronic properties. We find that substitutionally doped CNTs produce Ohmic contacts and that scattering at the interface is strongly influenced by structure. In addition, we consider the effect of the common vacancy defects on the electronic properties of large diameter CNTs. Defects increase scattering in the CNT, with the greatest scattering occurring for the largest defect (555777). We validate the independent scattering approximation for small diameter CNTs, which enables mean free paths in large diameter CNTs to be calculated, with a smaller mean free paths found for larger defects.

High speed nonlinear optical components for next-generation optical communications

Electronic signal processing systems currently employed at core internet routers require huge amounts of power to operate and they may be unable to continue to satisfy consumer demand for more bandwidth without an inordinate increase in cost, size and/or energy consumption. Optical signal processing techniques may be deployed in next-generation optical networks for simple tasks such as wavelength conversion, demultiplexing and format conversion at high speed (≥100Gb.s-1) to alleviate the pressure on existing core router infrastructure. To implement optical signal processing functionalities, it is necessary to exploit the nonlinear optical properties of suitable materials such as III-V semiconductor compounds, silicon, periodically-poled lithium niobate (PPLN), highly nonlinear fibre (HNLF) or chalcogenide glasses. However, nonlinear optical (NLO) components such as semiconductor optical amplifiers (SOAs), electroabsorption modulators (EAMs) and silicon nanowires are the most promising candidates as all-optical switching elements vis-à-vis ease of integration, device footprint and energy consumption. This PhD thesis presents the amplitude and phase dynamics in a range of device configurations containing SOAs, EAMs and/or silicon nanowires to support the design of all optical switching elements for deployment in next-generation optical networks. Time-resolved pump-probe spectroscopy using pulses with a pulse width of 3ps from mode-locked laser sources was utilized to accurately measure the carrier dynamics in the device(s) under test. The research work into four main topics: (a) a long SOA, (b) the concatenated SOA-EAMSOA (CSES) configuration, (c) silicon nanowires embedded in SU8 polymer and (d) a custom epitaxy design EAM with fast carrier sweepout dynamics. The principal aim was to identify the optimum operation conditions for each of these NLO device configurations to enhance their switching capability and to assess their potential for various optical signal processing functionalities. All of the NLO device configurations investigated in this thesis are compact and suitable for monolithic and/or hybrid integration.