Atomic layer deposition of interface control layers for the fabrication of III/V MOS devices

The continued advancement of metal oxide semiconductor field effect transistor (MOSFET) technology has shifted the focus from Si/SiO2 transistors towards high-κ/III-V transistors for high performance, faster devices. This has been necessary due to the limitations associated with the scaling of the SiO2 thickness below ~1 nm and the associated increased leakage current due to direct electron tunnelling through the gate oxide. The use of these materials exhibiting lower effective charge carrier mass in conjunction with the use of a high-κ gate oxide allows for the continuation of device scaling and increases in the associated MOSFET device performance. The high-κ/III-V interface is a critical challenge to the integration of high-κ dielectrics on III-V channels. The interfacial chemistry of the high-κ/III-V system is more complex than Si, due to the nature of the multitude of potential native oxide chemistries at the surface with the resultant interfacial layer showing poor electrical insulating properties when high-κ dielectrics are deposited directly on these oxides. It is necessary to ensure that a good quality interface is formed in order to reduce leakage and interface state defect density to maximise channel mobility and reduce variability and power dissipation. In this work, the ALD growth of aluminium oxide (Al2O3) and hafnium oxide (HfO2) after various surface pre-treatments was carried out, with the aim of improving the high-κ/III-V interface by reducing the Dit – the density of interface defects caused by imperfections such as dangling bonds, dimers and other unsatisfied bonds at the interfaces of materials. A brief investigation was performed into the structural and electrical properties of Al2O3 films deposited on In0.53Ga0.47As at 200 and 300oC via a novel amidinate precursor. Samples were determined to experience a severe nucleation delay when deposited directly on native oxides, leading to diminished functionality as a gate insulator due to largely reduced growth per cycle. Aluminium oxide MOS capacitors were prepared by ALD and the electrical characteristics of GaAs, In0.53Ga0.47As and InP capacitors which had been exposed to pre-pulse treatments from triethyl gallium and trimethyl indium were examined, to determine if self-cleaning reactions similar to those of trimethyl aluminium occur for other alkyl precursors. An improved C-V characteristic was observed for GaAs devices indicating an improved interface possibly indicating an improvement of the surface upon pre-pulsing with TEG, conversely degraded electrical characteristics observed for In0.53Ga0.47As and InP MOS devices after pre-treatment with triethyl gallium and trimethyl indium respectively. The electrical characteristics of Al2O3/In0.53Ga0.47As MOS capacitors after in-situ H2/Ar plasma treatment or in-situ ammonium sulphide passivation were investigated and estimates of interface Dit calculated. The use of plasma reduced the amount of interface defects as evidenced in the improved C-V characteristics. Samples treated with ammonium sulphide in the ALD chamber were found to display no significant improvement of the high-κ/III-V interface. HfO2 MOS capacitors were fabricated using two different precursors comparing the industry standard hafnium chloride process with deposition from amide precursors incorporating a ~1nm interface control layer of aluminium oxide and the structural and electrical properties investigated. Capacitors furnished from the chloride process exhibited lower hysteresis and improved C-V characteristics as compared to that of hafnium dioxide grown from an amide precursor, an indication that no etching of the film takes place using the chloride precursor in conjunction with a 1nm interlayer. Optimisation of the amide process was carried out and scaled samples electrically characterised in order to determine if reduced bilayer structures display improved electrical characteristics. Samples were determined to exhibit good electrical characteristics with a low midgap Dit indicative of an unpinned Fermi level

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.

Dilute nitride semiconductors : band structure, scattering and high field transport

The substitution of a small fraction x of nitrogen atoms, for the group V elements in conventional III-V semiconductors such as GaAs and GaSb strongly perturbs the conduction band of the host semiconductor. In this thesis we investigate the effects of nitrogen states on the band dispersion, carrier scattering and mobility of dilute nitride alloys. In the supercell model we solve the single particle Hamiltonian for a very large supercell containing randomly placed nitrogen. This model predicts a gap in the density of states of GaNxAs1−x, where this gap is filled in the Green’s function model. Therefore we develop a self-consistent Green’s function (SCGF) approach, which provides excellent agreement with supercell calculations and reveals a gap in the DOS, in contrast with the results of previous non-self-consistent Green’s function calculations. However, including the distribution of N states destroys this gap, as seen in experiment. We then examine the high field transport of carriers by solving the steadystate Boltzmann transport equation and find that it is necessary to include the full distribution of N levels in order to account for the small, low-field mobility and the absence of a negative differential velocity regime observed experimentally with increasing x. Overall the results account well for a wide range of experimental data. We also investigate the band structure, scattering and mobility of carriers by finding the poles of the SCGF, which gives lower carrier mobility for GaNxAs1−x, compared to those already calculated, in better agreement with experiments. The calculated optical absorption spectra for InyGa1−yNxAs1−x and GaNxSb1−x using the SCGF agree well with the experimental data, confirming the validity of this approach to study the band structure of these materials.

First principles modelling of nucleation and growth during atomic layer deposition onto III-V substrates

Atomic layer deposition (ALD) is now used in semiconductor fabrication lines to deposit nanometre-thin oxide films, and has thus enabled the introduction of high-permittivity dielectrics into the CMOS gate stack. With interest increasing in transistors based on high mobility substrates, such as GaAs, we are investigating the surface treatments that may improve the interface characteristics. We focus on incubation periods of ALD processes on III-V substrates. We have applied first principles Density Functional Theory (DFT) to investigate detailed chemistry of these early stages of growth, specifically substrate and ALD precursor interaction. We have modelled the ‘clean-up’ effect by which organometallic precursors: trimethylaluminium (TMA) or hafnium and titanium amides clean arsenic oxides off the GaAs surface before ALD growth of dielectric commences and similar effect on Si3N4 substrate. Our simulations show that ‘clean-up’ of an oxide film strongly depends on precursor ligand, its affinity to the oxide and the redox character of the oxide. The predominant pathway for a metalloid oxide such as arsenic oxide is reduction, producing volatile molecules or gettering oxygen from less reducible oxides. An alternative pathway is non-redox ligand exchange, which allows non-reducible oxides (e.g. SiO2) to be cleaned-up. First principles study shows also that alkylamides are more susceptible to decomposition rather than migration on the oxide surface. This improved understanding of the chemical principles underlying ‘clean-up’ allows us to rationalize and predict which precursors will perform the reaction. The comparison is made between selection of metal chlorides, methyls and alkylamides precursors.

Investigation of electrically active defects at the interface of high-k dielectrics and compound semiconductors

As silicon based devices in integrated circuits reach the fundamental limits of dimensional scaling there is growing research interest in the use of high electron mobility channel materials, such as indium gallium arsenide (InGaAs), in conjunction with high dielectric constant (high-k) gate oxides, for Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) based devices. The motivation for employing high mobility channel materials is to reduce power dissipation in integrated circuits while also providing improved performance. One of the primary challenges to date in the field of III-V semiconductors has been the observation of high levels of defect densities at the high-k/III-V interface, which prevents surface inversion of the semiconductor. The work presented in this PhD thesis details the characterization of MOS devices incorporating high-k dielectrics on III-V semiconductors. The analysis examines the effect of modifying the semiconductor bandgap in MOS structures incorporating InxGa1-xAs (x: 0, 0.15. 0.3, 0.53) layers, the optimization of device passivation procedures designed to reduce interface defect densities, and analysis of such electrically active interface defect states for the high-k/InGaAs system. Devices are characterized primarily through capacitance-voltage (CV) and conductance-voltage (GV) measurements of MOS structures both as a function of frequency and temperature. In particular, the density of electrically active interface states was reduced to the level which allowed the observation of true surface inversion behavior in the In0.53Ga0.47As MOS system. This was achieved by developing an optimized (NH4)2S passivation, minimized air exposure, and atomic layer deposition of an Al2O3 gate oxide. An extraction of activation energies allows discrimination of the mechanisms responsible for the inversion response. Finally a new approach is described to determine the minority carrier generation lifetime and the oxide capacitance in MOS structures. The method is demonstrated for an In0.53Ga0.47As system, but is generally applicable to any MOS structure exhibiting a minority carrier response in inversion.

A tight-binding analysis of the electronic properties of III-nitride semiconductors

This thesis divides into two distinct parts, both of which are underpinned by the tight-binding model. The first part covers our implementation of the tight-binding model in conjunction with the Berry phase theory of electronic polarisation to probe the atomistic origins of spontaneous polarisation and piezoelectricity as well as attempting to accurately calculate the values and coefficients associated with these phenomena. We first develop an analytic model for the polarisation of a one-dimensional linear chain of atoms. We compare the zincblende and ideal wurtzite structures in terms of effective charges, spontaneous polarisation and piezoelectric coefficients, within a first nearest neighbour tight-binding model. We further compare these to real wurtzite structures and conclude that accurate quantitative results are beyond the scope of this model but qualitative trends can still be described. The second part of this thesis deals with implementing the tight-binding model to investigate the effect of local alloy fluctuations in bulk AlGaN alloys and InGaN quantum wells. We calculate the band gap evolution of Al1_xGaxN across the full composition range and compare it to experiment as well as fitting bowing parameters to the band gap as well as to the conduction band and valence band edges. We also investigate the wavefunction character of the valence band edge to determine the composition at which the optical polarisation switches in Al1_xGaxN alloys. Finally, we examine electron and hole localisation in InGaN quantum wells. We show how the built-in field localises the carriers along the c-axis and how local alloy fluctuations strongly localise the highest hole states in the c-plane, while the electrons remain delocalised in the c-plane. We show how this localisation affects the charge density overlap and also investigate the effect of well width fluctuations on the localisation of the electrons.

An investigation by AFM and TEM of the mechanism of anodic formation of nanoporosity in n-InP in KOH

The early stages of nanoporous layer formation, under anodic conditions in the absence of light, were investigated for n-type InP with a carrier concentration of ∼3× 1018 cm-3 in 5 mol dm-3 KOH and a mechanism for the process is proposed. At potentials less than ∼0.35 V, spectroscopic ellipsometry and transmission electron microscopy (TEM) showed a thin oxide film on the surface. Atomic force microscopy (AFM) of electrode surfaces showed no pitting below ∼0.35 V but clearly showed etch pit formation in the range 0.4-0.53 V. The density of surface pits increased with time in both linear potential sweep and constant potential reaching a constant value at a time corresponding approximately to the current peak in linear sweep voltammograms and current-time curves at constant potential. TEM clearly showed individual nanoporous domains separated from the surface by a dense ∼40 nm InP layer. It is concluded that each domain develops as a result of directionally preferential pore propagation from an individual surface pit which forms a channel through this near-surface layer. As they grow larger, domains meet, and the merging of multiple domains eventually leads to a continuous nanoporous sub-surface region.

Anodic formation and characterization of nanoporous InP in aqueous KOH electrolytes

The anodic behavior of highly doped (> 1018 cm-3) n-InP in aqueous KOH was investigated. Electrodes anodized in the absence of light in 2- 5 mol dm-3 KOH at a constant potential of 0.5- 0.75 V (SCE), or subjected to linear potential sweeps to potentials in this range, were shown to exhibit the formation of a nanoporous subsurface region. Both linear sweep voltammograms and current-time curves at constant potential showed a characteristic anodic peak, corresponding to formation of the nanoporous region. No porous region was formed during anodization in 1 mol dm-3 KOH. The nanoporous region was examined using transmission electron microscopy and found to have a thickness of some 1- 3 μm depending on the anodization conditions and to be located beneath a thin (typically ∼40 nm), dense, near-surface layer. The pores varied in width from 25 to 75 nm and both the pore width and porous region thickness were found to decrease with increasing KOH concentration. The porosity was approximately 35%. The porous layer structure is shown to form by the localized penetration of surface pits into the InP, and the dense, near-surface layer is consistent with the effect of electron depletion at the surface of the semiconductor.

Role of substrate quality on the performance of semipolar (11 2 - 2) InGaN light-emitting diodes

We compare the optical properties and device performance of unpackaged InGaN/GaN multiple-quantum-well light-emitting diodes (LEDs) emitting at ∼430 nm grown simultaneously on a high-cost small-size bulk semipolar (11 2 - 2) GaN substrate (Bulk-GaN) and a low-cost large-size (11 2 - 2) GaN template created on patterned (10 1 - 2) r-plane sapphire substrate (PSS-GaN). The Bulk-GaN substrate has the threading dislocation density (TDD) of ∼ and basal-plane stacking fault (BSF) density of 0 cm-1, while the PSS-GaN substrate has the TDD of ∼2 × 108cm-2 and BSF density of ∼1 × 103cm-1. Despite an enhanced light extraction efficiency, the LED grown on PSS-GaN has two-times lower internal quantum efficiency than the LED grown on Bulk-GaN as determined by photoluminescence measurements. The LED grown on PSS-GaN substrate also has about two-times lower output power compared to the LED grown on Bulk-GaN substrate. This lower output power was attributed to the higher TDD and BSF density.

Development of germanium/silicon integration for near infrared detection

Silicon (Si) is the base material for electronic technologies and is emerging as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Applications for PICs are in the area of fibre-optic communication, biomedical devices, photovoltaics and imaging. Germanium (Ge), due to its suitable bandgap for telecommunications and its compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. There are two main approaches for Ge/Si integration: through epitaxial growth and through direct wafer bonding. The lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique which leads to a high density of dislocations while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in trap states which are expected to play a critical role. Understanding the physics of the interface is a key contribution of this thesis. This thesis investigates Ge/Si diodes using these two methods. The effects of interface traps on the static and dynamic performance of Ge/Si avalanche photodetectors have been modelled for the first time. The thesis outlines the original process development and characterization of mesa diodes which were fabricated by transferring a ~700 nm thick layer of p-type Ge onto n-type Si using direct wafer bonding and layer exfoliation. The effects of low temperature annealing on the device performance and on the conductivity of the interface have been investigated. It is shown that the diode ideality factor and the series resistance of the device are reduced after annealing. The carrier transport mechanism is shown to be dominated by generation–recombination before annealing and by direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing. The thesis presents a novel technique to realise photodetectors where one of the substrates is thinned by chemical mechanical polishing (CMP) after bonding the Si-Ge wafers. Based on this technique, Ge/Si detectors with remarkably high responsivities, in excess of 3.5 A/W at 1.55 μm at −2 V, under surface normal illumination have been measured. By performing electrical and optical measurements at various temperatures, the carrier transport through the hetero-interface is analysed by monitoring the Ge band bending from which a detailed band structure of the Ge/Si interface is proposed for the first time. The above unity responsivity of the detectors was explained by light induced potential barrier lowering at the interface. To our knowledge this is the first report of light-gated responsivity for vertically illuminated Ge/Si photodiodes. The wafer bonding approach followed by layer exfoliation or by CMP is a low temperature wafer scale process. In principle, the technique could be extended to other materials such as Ge on GaAs, or Ge on SOI. The unique results reported here are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout units in the form of 2D arrays of detectors. One potential future application is a low-cost Si process-compatible near infrared camera.

High speed nonlinear optical components for next-generation optical communications

Electronic signal processing systems currently employed at core internet routers require huge amounts of power to operate and they may be unable to continue to satisfy consumer demand for more bandwidth without an inordinate increase in cost, size and/or energy consumption. Optical signal processing techniques may be deployed in next-generation optical networks for simple tasks such as wavelength conversion, demultiplexing and format conversion at high speed (≥100Gb.s-1) to alleviate the pressure on existing core router infrastructure. To implement optical signal processing functionalities, it is necessary to exploit the nonlinear optical properties of suitable materials such as III-V semiconductor compounds, silicon, periodically-poled lithium niobate (PPLN), highly nonlinear fibre (HNLF) or chalcogenide glasses. However, nonlinear optical (NLO) components such as semiconductor optical amplifiers (SOAs), electroabsorption modulators (EAMs) and silicon nanowires are the most promising candidates as all-optical switching elements vis-à-vis ease of integration, device footprint and energy consumption. This PhD thesis presents the amplitude and phase dynamics in a range of device configurations containing SOAs, EAMs and/or silicon nanowires to support the design of all optical switching elements for deployment in next-generation optical networks. Time-resolved pump-probe spectroscopy using pulses with a pulse width of 3ps from mode-locked laser sources was utilized to accurately measure the carrier dynamics in the device(s) under test. The research work into four main topics: (a) a long SOA, (b) the concatenated SOA-EAMSOA (CSES) configuration, (c) silicon nanowires embedded in SU8 polymer and (d) a custom epitaxy design EAM with fast carrier sweepout dynamics. The principal aim was to identify the optimum operation conditions for each of these NLO device configurations to enhance their switching capability and to assess their potential for various optical signal processing functionalities. All of the NLO device configurations investigated in this thesis are compact and suitable for monolithic and/or hybrid integration.

Novel processes, test structures and characterisation for future germanium technologies

In order to widely use Ge and III-V materials instead of Si in advanced CMOS technology, the process and integration of these materials has to be well established so that their high mobility benefit is not swamped by imperfect manufacturing procedures. In this dissertation number of key bottlenecks in realization of Ge devices are investigated; We address the challenge of the formation of low resistivity contacts on n-type Ge, comparing conventional and advanced rapid thermal annealing (RTA) and laser thermal annealing (LTA) techniques respectively. LTA appears to be a feasible approach for realization of low resistivity contacts with an incredibly sharp germanide-substrate interface and contact resistivity in the order of 10 -7 Ω.cm2. Furthermore the influence of RTA and LTA on dopant activation and leakage current suppression in n+/p Ge junction were compared. Providing very high active carrier concentration > 1020 cm-3, LTA resulted in higher leakage current compared to RTA which provided lower carrier concentration ~1019 cm-3. This is an indication of a trade-off between high activation level and junction leakage current. High ION/IOFF ratio ~ 107 was obtained, which to the best of our knowledge is the best reported value for n-type Ge so far. Simulations were carried out to investigate how target sputtering, dose retention, and damage formation is generated in thin-body semiconductors by means of energetic ion impacts and how they are dependent on the target physical material properties. Solid phase epitaxy studies in wide and thin Ge fins confirmed the formation of twin boundary defects and random nucleation growth, like in Si, but here 600 °C annealing temperature was found to be effective to reduce these defects. Finally, a non-destructive doping technique was successfully implemented to dope Ge nanowires, where nanowire resistivity was reduced by 5 orders of magnitude using PH3 based in-diffusion process.

Theory of the electronic and optical properties of dilute bismide alloys

Dilute bismide alloys, containing small fractions of bismuth (Bi), have recently attracted interest due to their potential for applications in a range of semiconductor devices. Experiments have revealed that dilute bismide alloys such as GaBixAs1−x, in which a small fraction x of the atoms in the III-V semiconductor GaAs are replaced by Bi, exhibit a number of unusual and unique properties. For example, the band gap energy (E g) decreases rapidly with increasing Bi composition x, by up to 90 meV per % Bi replacing As in the alloy. This band gap reduction is accompanied by a strong increase in the spin-orbit-splitting energy (ΔSO) with increasing x, and both E g and ΔSO are characterised by strong, composition-dependent bowing. The existence of a ΔSO > E g regime in the GaBixAs1−x alloy has been demonstrated for x ≳10%, a band structure condition which is promising for the development of highly efficient, temperature stable semiconductor lasers that could lead to large energy savings in future optical communication networks. In addition to their potential for specific applications, dilute bismide alloys have also attracted interest from a fundamental perspective due to their unique properties. In this thesis we develop the theory of the electronic and optical properties of dilute bismide alloys. By adopting a multi-scale approach encompassing atomistic calculations of the electronic structure using the semi-empirical tight-binding method, as well as continuum calculations based on the k•p method, we develop a fundamental understanding of this unusual class of semiconductor alloys and identify general material properties which are promising for applications in semiconductor optoelectronic and photovoltaic devices. By performing detailed supercell calculations on both ordered and disordered alloys we explicitly demonstrate that Bi atoms act as isovalent impurities when incorporated in dilute quantities in III-V (In)GaAs(P) materials, strongly perturbing the electronic structure of the valence band. We identify and quantify the causes and consequences of the unusual electronic properties of GaBixAs1−x and related alloys, and our analysis is reinforced throughout by a series of detailed comparisons to the results of experimental measurements. Our k•p models of the band structure of GaBixAs1−x and related alloys, which we derive directly from detailed atomistic calculations, are ideally suited to the study of dilute bismide-based devices. We focus in the latter part of the thesis on calculations of the electronic and optical properties of dilute bismide quantum well lasers. In addition to developing an understanding of the effects of Bi incorporation on the operational characteristics of semiconductor lasers, we also present calculations which have been used explicitly in designing and optimising the first generation of GaBixAs1−x-based devices.

Organic functionalisation, doping and characterisation of semiconductor surfaces for future CMOS device applications

Organic Functionalisation, Doping and Characterisation of Semiconductor Surfaces for Future CMOS Device Applications Semiconductor materials have long been the driving force for the advancement of technology since their inception in the mid-20th century. Traditionally, micro-electronic devices based upon these materials have scaled down in size and doubled in transistor density in accordance with the well-known Moore’s law, enabling consumer products with outstanding computational power at lower costs and with smaller footprints. According to the International Technology Roadmap for Semiconductors (ITRS), the scaling of metal-oxide-semiconductor field-effect transistors (MOSFETs) is proceeding at a rapid pace and will reach sub-10 nm dimensions in the coming years. This scaling presents many challenges, not only in terms of metrology but also in terms of the material preparation especially with respect to doping, leading to the moniker “More-than-Moore”. Current transistor technologies are based on the use of semiconductor junctions formed by the introduction of dopant atoms into the material using various methodologies and at device sizes below 10 nm, high concentration gradients become a necessity. Doping, the controlled and purposeful addition of impurities to a semiconductor, is one of the most important steps in the material preparation with uniform and confined doping to form ultra-shallow junctions at source and drain extension regions being one of the key enablers for the continued scaling of devices. Monolayer doping has shown promise to satisfy the need to conformally dope at such small feature sizes. Monolayer doping (MLD) has been shown to satisfy the requirements for extended defect-free, conformal and controllable doping on many materials ranging from the traditional silicon and germanium devices to emerging replacement materials such as III-V compounds This thesis aims to investigate the potential of monolayer doping to complement or replace conventional doping technologies currently in use in CMOS fabrication facilities across the world.

Hybrid integration and packaging of grating-coupled silicon photonics

This thesis covers both the packaging of silicon photonic devices with fiber inputs and outputs as well as the integration of laser light sources with these same devices. The principal challenge in both of these pursuits is coupling light into the submicrometer waveguides that are the hallmark of silicon-on-insulator (SOI) systems. Previous work on grating couplers is leveraged to design new approaches to bridge the gap between the highly-integrated domain of silicon, the Interconnected world of fiber and the active region of III-V materials. First, a novel process for the planar packaging of grating couplers with fibers is explored in detail. This technology allows the creation of easy-to-use test platforms for laser integration and also stands on its own merits as an enabling technology for next-generation silicon photonics systems. The alignment tolerances of this process are shown to be well-suited to a passive alignment process and for wafer-scale assembly. Furthermore, this technology has already been used to package demonstrators for research partners and is included in the offerings of the ePIXfab silicon photonics foundry and as a design kit for PhoeniX Software’s MaskEngineer product. After this, a process for hybridly integrating a discrete edge-emitting laser with a silicon photonic circuit using near-vertical coupling is developed and characterized. The details of the various steps of the design process are given, including mechanical, thermal, optical and electrical steps. The interrelation of these design domains is also discussed. The construction process for a demonstrator is outlined, and measurements are presented of a series of single-wavelength Fabry-Pérot lasers along with a two-section laser tunable in the telecommunications C-band. The suitability and potential of this technology for mass manufacture is demonstrated, with further opportunities for improvement detailed and discussed in the conclusion.