A planar reconfigurable linear rigid-body motion linkage with two operation modes

A planar reconfigurable linear (also rectilinear) rigid-body motion linkage (RLRBML) with two operation modes, that is, linear rigid-body motion mode and lockup mode, is presented using only R (revolute) joints. The RLRBML does not require disassembly and external intervention to implement multi-task requirements. It is created via combining a Robert’s linkage and a double parallelogram linkage (with equal lengths of rocker links) arranged in parallel, which can convert a limited circular motion to a linear rigid-body motion without any reference guide way. This linear rigid-body motion is achieved since the double parallelogram linkage can guarantee the translation of the motion stage, and Robert’s linkage ensures the approximate straight line motion of its pivot joint connecting to the double parallelogram linkage. This novel RLRBML is under the linear rigid-body motion mode if the four rocker links in the double parallelogram linkage are not parallel. The motion stage is in the lockup mode if all of the four rocker links in the double parallelogram linkage are kept parallel in a tilted position (but the inner/outer two rocker links are still parallel). In the lockup mode, the motion stage of the RLRBML is prohibited from moving even under power off, but the double parallelogram linkage is still moveable for its own rotation application. It is noted that further RLRBMLs can be obtained from the above RLRBML by replacing Robert’s linkage with any other straight line motion linkage (such as Watt’s linkage). Additionally, a compact RLRBML and two single-mode linear rigid-body motion linkages are presented.

SDN enabled dynamically reconfigurable high capacity optical access architecture for converged services

Dynamically reconfigurable time-division multiplexing (TDM) dense wavelength division multiplexing (DWDM) long-reach passive optical networks (PONs) can support the reduction of nodes and network interfaces by enabling a fully meshed flat optical core. In this paper we demonstrate the flexibility of the TDM-DWDM PON architecture, which can enable the convergence of multiple service types on a single physical layer. Heterogeneous services and modulation formats, i.e. residential 10G PON channels, business 100G dedicated channel and wireless fronthaul, are demonstrated co-existing on the same long reach TDM-DWDM PON system, with up to 100km reach, 512 users and emulated system load of 40 channels, employing amplifier nodes with either erbium doped fiber amplifiers (EDFAs) or semiconductor optical amplifiers (SOAs). For the first time end-to-end software defined networking (SDN) management of the access and core network elements is also implemented and integrated with the PON physical layer in order to demonstrate two service use cases: a fast protection mechanism with end-to-end service restoration in the case of a primary link failure; and dynamic wavelength allocation (DWA) in response to an increased traffic demand.

Hardware processors for pairing-based cryptography

Bilinear pairings can be used to construct cryptographic systems with very desirable properties. A pairing performs a mapping on members of groups on elliptic and genus 2 hyperelliptic curves to an extension of the finite field on which the curves are defined. The finite fields must, however, be large to ensure adequate security. The complicated group structure of the curves and the expensive field operations result in time consuming computations that are an impediment to the practicality of pairing-based systems. The Tate pairing can be computed efficiently using the ɳT method. Hardware architectures can be used to accelerate the required operations by exploiting the parallelism inherent to the algorithmic and finite field calculations. The Tate pairing can be performed on elliptic curves of characteristic 2 and 3 and on genus 2 hyperelliptic curves of characteristic 2. Curve selection is dependent on several factors including desired computational speed, the area constraints of the target device and the required security level. In this thesis, custom hardware processors for the acceleration of the Tate pairing are presented and implemented on an FPGA. The underlying hardware architectures are designed with care to exploit available parallelism while ensuring resource efficiency. The characteristic 2 elliptic curve processor contains novel units that return a pairing result in a very low number of clock cycles. Despite the more complicated computational algorithm, the speed of the genus 2 processor is comparable. Pairing computation on each of these curves can be appealing in applications with various attributes. A flexible processor that can perform pairing computation on elliptic curves of characteristic 2 and 3 has also been designed. An integrated hardware/software design and verification environment has been developed. This system automates the procedures required for robust processor creation and enables the rapid provision of solutions for a wide range of cryptographic applications.