Energy harvesting embedded wireless sensor system for building environment applications

For many wireless sensor networks applications, indoor light energy is the only ambient energy source commonly available. Many advantages and constraints co-exist in this technology. However, relatively few indoor light powered harvesters have been presented and much research remains to be carried out on a variety of related design considerations and trade-offs. This work presents a solution using the Tyndall mote and an indoor light powered wireless sensor node. It analyses design considerations on several issues such as indoor light characteristics, solar panel component choice, maximum power point tracking, energy storage elements and the trade-offs and choices between them.

Design and implementation of the embedded capacitance layers for decoupling of wireless sensor nodes

In this paper, the embedded capacitance material (ECM) is fabricated between the power and ground layers of the wireless sensor nodes, forming an integrated capacitance to replace the large amount of decoupling capacitors on the board. The ECM material, whose dielectric constant is 16, has the same size of the wireless sensor nodes of 3cm*3cm, with a thickness of only 14μm. Though the capacitance of a single ECM layer being only around 8nF, there are two reasons the ECM layers can still replace the high frequency decoupling capacitors (100nF in our case) on the board. The first reason is: the parasitic inductance of the ECM layer is much lower than the surface mount capacitors'. A smaller capacitance value of the ECM layer could achieve the same resonant frequency of the surface mount decoupling capacitors. Simulation and measurement fit this assumption well. The second reason is: more than one layer of ECM material are utilized during the design step to get a parallel connection of the several ECM capacitance layers, finally leading to a larger value of the capacitance and smaller value of parasitic. Characterization of the ECM is carried out by the LCR meter. To evaluate the behaviors of the ECM layer, time and frequency domain measurements are performed on the power-bus decoupling of the wireless sensor nodes. Comparison with the measurements of bare PCB board and decoupling capacitors solution are provided to show the improvement of the ECM layer. Measurements show that the implementation of the ECM layer can not only save the space of the surface mount decoupling capacitors, but also provide better power-bus decoupling to the nodes.

Cryptographic coprocessors for embedded systems

In the field of embedded systems design, coprocessors play an important role as a component to increase performance. Many embedded systems are built around a small General Purpose Processor (GPP). If the GPP cannot meet the performance requirements for a certain operation, a coprocessor can be included in the design. The GPP can then offload the computationally intensive operation to the coprocessor; thus increasing the performance of the overall system. A common application of coprocessors is the acceleration of cryptographic algorithms. The work presented in this thesis discusses coprocessor architectures for various cryptographic algorithms that are found in many cryptographic protocols. Their performance is then analysed on a Field Programmable Gate Array (FPGA) platform. Firstly, the acceleration of Elliptic Curve Cryptography (ECC) algorithms is investigated through the use of instruction set extension of a GPP. The performance of these algorithms in a full hardware implementation is then investigated, and an architecture for the acceleration the ECC based digital signature algorithm is developed. Hash functions are also an important component of a cryptographic system. The FPGA implementation of recent hash function designs from the SHA-3 competition are discussed and a fair comparison methodology for hash functions presented. Many cryptographic protocols involve the generation of random data, for keys or nonces. This requires a True Random Number Generator (TRNG) to be present in the system. Various TRNG designs are discussed and a secure implementation, including post-processing and failure detection, is introduced. Finally, a coprocessor for the acceleration of operations at the protocol level will be discussed, where, a novel aspect of the design is the secure method in which private-key data is handled

Solid-state synthesis of embedded single-crystal metal oxide and phosphate nanoparticles and in situ crystallization

A new solid state organometallic route to embedded nanoparticle-containing inorganic materials is shown, through pyrolysis of metal-containing derivatives of cyclotriphosphazenes. Pyrolysis in air and at 800 °C of new molecular precursors gives individual single-crystal nanoparticles of SiP2O7, TiO2, P4O7, WP2O7 and SiO2, depending on the precursor used. High resolution transmission electron microscopy investigations reveal, in most cases, perfect single crystals of metal oxides and the first nanostructures of negative thermal expansion metal phosphates with diameters in the range 2–6 nm for all products. While all nanoparticles are new by this method, WP2O7 and SiP2O7 nanoparticles are reported for the first time. In situ recrystallization formation of nanocrystals of SiP2O7 was also observed due to electron beam induced reactions during measurements of the nanoparticulate pyrolytic products SiO2 and P4O7. The possible mechanism for the formation of the nanoparticles at much lower temperatures than their bulk counterparts in both cases is discussed. Degrees of stabilization from the formation of P4O7 affects the nanocrystalline products: nanoparticles are observed for WP2O7, with coalescing crystallization occurring for the amorphous host in which SiP2O7 crystals form as a solid within a solid. The approach allows the simple formation of multimetallic, monometallic, metal-oxide and metal phosphate nanocrystals embedded in an amorphous dielectric. The method and can be extended to nearly any metal capable of successful coordination as an organometallic to allow embedded nanoparticle layers and features to be deposited or written on surfaces for application as high mobility pyrophosphate lithium–ion cathode materials, catalysis and nanocrystal embedded dielectric layers.

Optical emission of strained direct-band-gap Ge quantum well embedded inside InGaAs alloy layers

We studied the optical properties of a strain-induced direct-band-gap Ge quantum well embedded in InGaAs. We showed that the band offsets depend on the electronegativity of the layer in contact with Ge, leading to different types of optical transitions in the heterostructure. When group-V atoms compose the interfaces, only electrons are confined in Ge, whereas both carriers are confined when the interface consists of group-III atoms. The different carrier confinement results in different emission dynamics behavior. This study provides a solution to obtain efficient light emission from Ge.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.