'La Violence et la mauvaise foi': Context and rhetoric in Pierre Bayle's Ce que c'est que la France toute Catholique

My thesis presents an examination of Ce que c'est que la France toute Catholique (1686) by Pierre Bayle, a prominent figure in the Republic of Letters and the Huguenot Refuge in the seventeenth century. This pamphlet was the first occasional text that Bayle published following the Revocation of the Edict of Nantes in which the religious toleration afforded to the Huguenot minority in France was repealed, a pivotal moment in the history of early modern France. In my thesis, I analyse the specific context within which Bayle wrote this pamphlet as a means of addressing a number of issues, including the legitimacy of forced conversions, the impact of the religious controversy upon exchanges in the Republic of Letters, the nature of religious zeal and finally the alliance of Church and state discourses in the early modern period. An examination of this context provides a basis from which to re-interpret the rhetorical strategies at work within the pamphlet, and also to come to an increased understanding of how, why and to what end he wrote it. In turn this allowed me to examine the relationship between this often overlooked pamphlet and the more extensively studied Commentaire Philosophique, in which Bayle argued in favour of religious toleration. Ultimately, understanding the relationship between these two texts proves essential in order to characterise his response to the Revocation of the Edict of Nantes and to understand the place of the pamphlet within his oeuvre. Furthermore, an analysis of the pamphlet and the Commentaire Philosophique provide a lens through which to elucidate both Bayle's intellectual development at this early stage in his career, and also the wider context of the rise of toleration theory and the evolution of modes of civility within the Republic of Letters on the eve of the Enlightenment.

A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V.

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach.