High temperature limit in static backgrounds

We prove that the hard thermal loop contribution to static thermal amplitudes can be obtained by setting all the external four-momenta to zero before performing the Matsubara sums and loop integrals. At the one-loop order we do an iterative procedure for all the one-particle irreducible one-loop diagrams, and at the two-loop order we consider the self-energy. Our approach is sufficiently general to the extent that it includes theories with any kind of interaction vertices, such as gravity in the weak field approximation, for d space-time dimensions. This result is valid whenever the external fields are all bosonic.

Temperature impact on the tunnel fet off-state current components

In this work, the temperature impact on the off-state current components is analyzed through numerical simulation and experimentally. First of all, the band-to-band tunneling is studied by varying the underlap in the channel/drain junction, leading to an analysis of the different off-state current components. For pTFET devices, the best behavior for off-state current was obtained for higher values of underlap (reduced BTBT) and at low temperatures (reduced SRH and TAT). At high temperature, an unexpected off-state current occurred due to the thermal leakage current through the drain/channel junction. Besides, these devices presented a good performance when considering the drain current as a function of the drain voltage, making them suitable for analog applications. (C) 2012 Elsevier Ltd. All rights reserved.