LALP: a language to program custom FPGA-based acceleration engines

Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained with Application-Specific Integrated Circuits, while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers in order to master hardware description languages (HDLs) such as VHDL or Verilog. Attempts to furnish a high-level compilation flow (e.g., from C programs) still have to address open issues before broader efficient results can be obtained. Bearing in mind an FPGA available resources, it has been developed LALP (Language for Aggressive Loop Pipelining), a novel language to program FPGA-based accelerators, and its compilation framework, including mapping capabilities. The main ideas behind LALP are to provide a higher abstraction level than HDLs, to exploit the intrinsic parallelism of hardware resources, and to allow the programmer to control execution stages whenever the compiler techniques are unable to generate efficient implementations. Those features are particularly useful to implement loop pipelining, a well regarded technique used to accelerate computations in several application domains. This paper describes LALP, and shows how it can be used to achieve high-performance computing solutions.

Programmable logic design of a compact Genetic Algorithm for phasor estimation in real-time

The main objective of this work is to present an efficient method for phasor estimation based on a compact Genetic Algorithm (cGA) implemented in Field Programmable Gate Array (FPGA). To validate the proposed method, an Electrical Power System (EPS) simulated by the Alternative Transients Program (ATP) provides data to be used by the cGA. This data is as close as possible to the actual data provided by the EPS. Real life situations such as islanding, sudden load increase and permanent faults were considered. The implementation aims to take advantage of the inherent parallelism in Genetic Algorithms in a compact and optimized way, making them an attractive option for practical applications in real-time estimations concerning Phasor Measurement Units (PMUs).

Dendrimers/TiO2 nanoparticles layer-by-layer films as extended gate FET for pH detection

The layer-by-layer (LbL) technique combined with field-effect transistor (FET) based sensors has enabled the production of pH-sensitive platforms with potential application in biosensors. A variation of the FET architecture, so called separative extended gate FET (SEGFET) devices, are promise as an alternative to conventional ion sensitive FET (ISFET). SEGFET configuration exhibits the advantage of combining the field-effect concept with organic and inorganic materials directly adsorbed on the extended gate, allowing the test of new pH-sensitive materials in a simple and low cost way. In this communication, poly(propylene imine) dendrimer (PPI) and TiO2 nanoparticles (TiO2-np) were assembled onto gold-covered substrates via layer-by-layer technique to produce a low cost SEGFET pH sensor. The sensor presented good pH sensitivity, ca. 57 mV pH(-1), showing that our strategy has potential advantages to fabricate low cost pH-sensing membranes. (C) 2012 Elsevier B.V. All rights reserved.

Morphology and topography analysis of mesoporous titania templated by micrometric latex sphere arrays

In this work, mesoporous titania is prepared by templating latex sphere arrays with four different sphere diameters at the micrometric scale (phi > 1 mu m). The mesoporous titania homogeneously covers the latex spheres and substrate, forming a thin coating characterized by N-2 adsorption isotherm, small angle X-rays scattering, atomic force, field emission and transmission electronic microscopies. Mesoporous titania has been templated into different shapes such as hollow particles and monoliths according to the amount of sol used to fill the voids of the close packed latex spheres. Titania topography strongly depends on the adsorption of polymeric segments over latex spheres surface, which could be decreased by changing the dimensions of latex spheres (phi = 9.5 mu m) generating a lamellar architecture. Thus, micrometric latex sphere arrays can be used to achieve new surface patterns for mesoporous materials via a fast and inexpensive chemical route for construction of functional devices in different technological fields such as energy conversion, inclusion chemistry and biomaterials. (C) 2011 Elsevier Inc. All rights reserved.

Electrical characterization of poly(amide-imide) for application in organic field effect devices

The admittance spectra and current-voltage (I-V) characteristics are reported of metal-insulator-metal (MIM) and metal-insulator-semiconductor (MIS) capacitors employing cross-linked poly(amide-imide) (c-PAI) as the insulator and poly(3-hexylthiophene) (P3HT) as the active semiconductor. The capacitance of the MIM devices are constant in the frequency range from 10 Hz to 100 kHz, with tan delta values as low as 7 x 10(-3) over most of the range. Except at the lowest voltages, the I-V characteristics are well-described by the Schottky equation for thermal emission of electrons from the electrodes into the insulator. The admittance spectra of the MIS devices displayed a classic Maxwell-Wagner frequency response from which the transverse bulk hole mobility was estimated to be similar to 2 x 10(-5) cm(2) V(-1)s(-1) or similar to 5 x 10(-8) cm(2) V(-1)s(-1) depending on whether or not the surface of the insulator had been treated with hexamethyldisilazane (HMDS) prior to deposition of the P3HT. From the maximum loss observed in admittance-voltage plots, the interface trap density was estimated to be similar to 5 x 10(10) cm(-2) eV(-1) or similar to 9 x 10(10) cm(-2) eV(-1) again depending whether or not the insulator was treated with HMDS. We conclude, therefore, that HMDS plays a useful role in promoting order in the P3HT film as well as reducing the density of interface trap states. Although interposing the P3HT layer between the insulator and the gold electrode degrades the insulating properties of the c-PAI, nevertheless, they remain sufficiently good for use in organic electronic devices. (c) 2012 Elsevier B.V. All rights reserved.

GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL On the other hand, the impact of the gate dielectric on the GIDL for p-channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed. (C) 2011 Elsevier Ltd. All rights reserved.