Controladores repetitivos aplicados a filtros ativos de potência sob variações de carga e de frequência da rede

This work presents the development and modification of techniques to reduce the effects of load variation and mains frequency deviation in repetitive controllers applied to active power filters. To minimize the effects of aperiodic signals resulting from the connection or disconnection of non-linear loads is developed a technique which recognizes linear and nonlinear loads, and operates to reset the controller only when the error due to the transition of considerable value, and the transition is from non-linear to linear load. An algorithm to adapt the gain of the repetitive controller, based on a sigmoid function adaptation, in order to minimize the effects caused by random noise in the measurement system is also used. This work also analyzes the effects of frequency variation and presents the main methods to cope with this situation. Some solutions are the change in the number of samples per period and the variation of the sampling rate. The first has the advantage of using linear design techniques and results in a time invariant system. The second method changes the sampling frequency and leads to a time variant system that demands a difficult analysis of stability. The proposed algorithms were tested using the methods of truncation of the number of samples and the method of changing the sampling rate of the system to compensate possible frequency variations of the grid. Experimental results are presented to validate the proposal.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

Comparação do controle do inversor trifásico conectado à rede com filtro LCL considerando o amortecimento passivo e ativo

Distributed generation systems must fulfill standards specifications of current harmonics injected to the grid. In order to satisfy these grid requirements, passive filters are connected between inverter and grid. This work compares the characteristic response of the traditional inductive (L) filter with the inductive-capacitive-inductive (LCL) filter. It is shown that increasing the inductance L leads to a good ripple current suppression around the inverter switching frequency. The LCL filter provides better harmonic attenuation and reduces the filter size. The main drawback is the LCL filter impedance, which is characterized by a typical resonance peak, which must be damped to avoid instability. Passive or active techniques can be used to damp the LCL resonance. To address this issue, this dissertation presents a comparison of current control for PV grid-tied inverters with L filter and LCL filter and also discuss the use of active and passive damping for different regions of resonance frequency. From the mathematical models, a design methodology of the controllers was developed and the dynamic behavior of the system operating in closed loop was investigated. To validate the studies developed during this work, experimental results are presented using a three-phase 5kW experimental platform. The main components and their functions are discussed in this work. Experimental results are given to support the theoretical analysis and to illustrate the performance of grid-connected PV inverter system. It is shown that the resonant frequency of the system, and sampling frequency can be associated in order to calculate a critical frequency, below which is essential to perform the damping of the LCL filter. Also, the experimental results show that the active buffer per virtual resistor, although with a simple development, is effective to damp the resonance of the LCL filter and allow the system to operate stable within predetermined parameters.

Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado

This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.