Diagnóstico automático de eventos e distúrbios em unidades geradoras e usinas utilizando lógica fuzzy

The electric power systems are getting more complex and covering larger areas day by day. This fact has been contribuiting to the development of monitoring techniques that aim to help the analysis, control and planning of power systems. Supervisory Control and Data Acquisition (SCADA) systems, Wide Area Measurement Systems and disturbance record systems. Unlike SCADA and WAMS, disturbance record systems are mainly used for offilne analysis in occurrences where a fault resulted in tripping of and apparatus such as a transimission line, transformer, generator and so on. The device responsible for record the disturbances is called Digital Fault Recorder (DFR) and records, basically, electrical quantities as voltage and currents and also, records digital information from protection system devices. Generally, in power plants, all the DFRs data are centralized in the utility data centre and it results in an excess of data that difficults the task of analysis by the specialist engineers. This dissertation shows a new methodology for automated analysis of disturbances in power plants. A fuzzy reasoning system is proposed to deal with the data from the DFRs. The objective of the system is to help the engineer resposnible for the analysis of the DFRs’s information by means of a pre-classification of data. For that, the fuzzy system is responsible for generating unit operational state diagnosis and fault classification.

Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado

This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.