4 resultados para Compensação seletiva

em Repositório Institucional da Universidade Tecnológica Federal do Paraná (RIUT)


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This work presents the development and modification of techniques to reduce the effects of load variation and mains frequency deviation in repetitive controllers applied to active power filters. To minimize the effects of aperiodic signals resulting from the connection or disconnection of non-linear loads is developed a technique which recognizes linear and nonlinear loads, and operates to reset the controller only when the error due to the transition of considerable value, and the transition is from non-linear to linear load. An algorithm to adapt the gain of the repetitive controller, based on a sigmoid function adaptation, in order to minimize the effects caused by random noise in the measurement system is also used. This work also analyzes the effects of frequency variation and presents the main methods to cope with this situation. Some solutions are the change in the number of samples per period and the variation of the sampling rate. The first has the advantage of using linear design techniques and results in a time invariant system. The second method changes the sampling frequency and leads to a time variant system that demands a difficult analysis of stability. The proposed algorithms were tested using the methods of truncation of the number of samples and the method of changing the sampling rate of the system to compensate possible frequency variations of the grid. Experimental results are presented to validate the proposal.

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The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

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The purpose of this work is to demonstrate and to assess a simple algorithm for automatic estimation of the most salient region in an image, that have possible application in computer vision. The algorithm uses the connection between color dissimilarities in the image and the image’s most salient region. The algorithm also avoids using image priors. Pixel dissimilarity is an informal function of the distance of a specific pixel’s color to other pixels’ colors in an image. We examine the relation between pixel color dissimilarity and salient region detection on the MSRA1K image dataset. We propose a simple algorithm for salient region detection through random pixel color dissimilarity. We define dissimilarity by accumulating the distance between each pixel and a sample of n other random pixels, in the CIELAB color space. An important result is that random dissimilarity between each pixel and just another pixel (n = 1) is enough to create adequate saliency maps when combined with median filter, with competitive average performance if compared with other related methods in the saliency detection research field. The assessment was performed by means of precision-recall curves. This idea is inspired on the human attention mechanism that is able to choose few specific regions to focus on, a biological system that the computer vision community aims to emulate. We also review some of the history on this topic of selective attention.

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This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.