Controladores repetitivos aplicados a filtros ativos de potência sob variações de carga e de frequência da rede

This work presents the development and modification of techniques to reduce the effects of load variation and mains frequency deviation in repetitive controllers applied to active power filters. To minimize the effects of aperiodic signals resulting from the connection or disconnection of non-linear loads is developed a technique which recognizes linear and nonlinear loads, and operates to reset the controller only when the error due to the transition of considerable value, and the transition is from non-linear to linear load. An algorithm to adapt the gain of the repetitive controller, based on a sigmoid function adaptation, in order to minimize the effects caused by random noise in the measurement system is also used. This work also analyzes the effects of frequency variation and presents the main methods to cope with this situation. Some solutions are the change in the number of samples per period and the variation of the sampling rate. The first has the advantage of using linear design techniques and results in a time invariant system. The second method changes the sampling frequency and leads to a time variant system that demands a difficult analysis of stability. The proposed algorithms were tested using the methods of truncation of the number of samples and the method of changing the sampling rate of the system to compensate possible frequency variations of the grid. Experimental results are presented to validate the proposal.

Projeto, implementação e análise de um conversor CC-CC de alto ganho e alto rendimento para aplicações fotovoltaicas

In recent years the photovoltaic generation has had greater insertion in the energy mix of the most developed countries, growing at annual rates of over 30%. The pressure for the reduction of pollutant emissions, diversification of the energy mix and the drop in prices are the main factors driving this growth. Grid tied systems plays an important role in alleviating the energy crisis and diversification of energy sources. Among the grid tied systems, building integrated photovoltaic systems suffers from partial shading of the photovoltaic modules and consequently the energy yield is reduced. In such cases, classical forms of modules connection do not produce good results and new techniques have been developed to increase the amount of energy produced by a set of modules. In the parallel connection technique of photovoltaic modules, a high voltage gain DC-DC converter is required, which is relatively complex to build with high efficiency. The current-fed isolated converters explored in this work have some desirable characteristics for this type of application, such as: low input current ripple and input voltage ripple, high voltage gain, galvanic isolation, feature high power capacity and it achieve soft switching in a wide operating range. This study presents contributions to the study of a high gain and high efficiency DC-DC converter for use in a parallel system of photovoltaic generation, being possible the use in a microinverter or with central inverter. The main contributions of this work are: analysis of the active clamping circuit operation proposing that the clamp capacitor connection must be done on the negative node of the power supply to reduce the input current ripple and thus reduce the filter requirements; use of a voltage doubler in the output rectifier to reduce the number of components and to extend the gain of the converter; detailed study of the converter components in order to raise the efficiency; obtaining the AC equivalent model and control system design. As a result, a DC-DC converter with high gain, high efficiency and without electrolytic capacitors in the power stage was developed. In the final part of this work the DC-DC converter operation connected to an inverter is presented. Besides, the DC bus controller is designed and are implemented two maximum power point tracking algorithms. Experimental results of full system operation connected to an emulator and subsequently to a real photovoltaic module are also given.

Análise e proposição de estratégias de estimação e controle de velocidade para motores de indução trifásicos

This study presents a proposal of speed servomechanisms without the use of mechanical sensors (sensorless) using induction motors. A comparison is performed and propose techniques for pet rotor speed, analyzing performance in different conditions of speed and load. For the determination of control technique, initially, is performed an analysis of the technical literature of the main control and speed estimation used, with their characteristics and limitations. The proposed technique for servo sensorless speed induction motor uses indirect field-oriented control (IFOC), composed of four controllers of the proportional-integral type (PI): rotor flux controller, speed controller and current controllers in the direct and quadrature shaft. As the main focus of the work is in the speed control loop was implemented in Matlab the recursive least squares algorithm (RLS) for identification of mechanical parameters, such as moment of inertia and friction coefficient. Thus, the speed of outer loop controller gains can be self adjusted to compensate for any changes in the mechanical parameters. For speed estimation techniques are analyzed: MRAS by rotóricos fluxes MRAS by counter EMF, MRAS by instantaneous reactive power, slip, locked loop phase (PLL) and sliding mode. A proposition of estimation in sliding mode based on speed, which is performed a change in rotor flux observer structure is displayed. To evaluate the techniques are performed theoretical analyzes in Matlab simulation environment and experimental platform in electrical machinery drives. The DSP TMS320F28069 was used for experimental implementation of speed estimation techniques and check the performance of the same in a wide speed range, including load insertion. From this analysis is carried out to implement closed-loop control of sensorless speed IFOC structure. The results demonstrated the real possibility of replacing mechanical sensors for estimation techniques proposed and analyzed. Among these, the estimator based on PLL demonstrated the best performance in various conditions, while the technique based on sliding mode has good capacity estimation in steady state and robustness to parametric variations.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.

Implementação em FPGA de compensadores de desvios para conversor analógico digital intercalado

This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.