Partial rectification of the plasmon-induced electrical tunnel current in discontinuous thin gold film at optical frequency

The effect of plasmonoscillations, induced by pulsed laserirradiation, on the DC tunnel current between islands in a discontinuous thin goldfilm is studied. The tunnel current is found to be strongly enhanced by partial rectification of the plasmon-induced AC tunnel currents flowing between adjacent gold islands. The DC tunnel current enhancement is found to increase approximately linearly with the laser intensity and the applied DC bias voltage. The experimental data can be well described by an electron tunnelling model which takes the plasmon-induced AC voltage into account. Thermal heating seems not to contribute to the tunnel current enhancement.

Demonstration of nonlinear absorption in Au semi-continuous film by electrical measurement

We have demonstrated the nonlinear absorption at 532 nm wavelength in an Au semi-continuous film (SF) resulting from smearing of the Fermi distribution and diffusion of conduction electrons into the substrate. The Au SF was irradiated by a pulsed laser with 8 ns pulse width at 532 nm in near resonance with the interband transition of the Au. We determined the temperature increase in the SF for different intensities by electrical measurement. We calculated the temperature increase by using a 1D heat transport equation; comparing the results of the calculation with measured values for the temperature increase, revealed the nonlinear absorption in the Au SF. We employed this deviation from linear behaviour to determine the nonlinear absorption coefficient.

Effect of Coulomb blockade, gold resistance, and thermal expansion on the electrical resistance of ultrathin gold films

Controlling the electrical resistance of granular thin films is of great importance for many applications, yet a full understanding of electron transport in such films remains a major challenge. We have studied experimentally and by model calculations the temperature dependence of the electrical resistance of ultrathin gold films at temperatures between 2 K and 300 K. Using sputter deposition, the film morphology was varied from a discontinuous film of weakly coupled meandering islands to a continuous film of strongly coupled coalesced islands. In the weak-coupling regime, we compare the regular island array model, the cotunneling model, and the conduction percolation model with our experimental data. We show that the tunnel barriers and the Coulomb blockade energies are important at low temperatures and that the thermal expansion of the substrate and the island resistance affect the resistance at high temperatures. At low temperatures our experimental data show evidence for a transition from electron cotunneling to sequential tunneling but the data can also be interpreted in terms of conduction percolation. The resistivity and temperature coefficient of resistance of the meandering gold islands are found to resemble those of gold nanowires. We derive a simple expression for the temperature at which the resistance changes from non-metal-like behavior into metal-like behavior. In the case of strong island coupling, the total resistance is solely determined by the Ohmic island resistance.

Thinning vertical graphenes, tuning electrical response : from semiconducting to metallic

A simple, uniquely plasma-enabled and environment-friendly process to reduce the thickness of vertically standing graphenes to only 4–5 graphene layers and arranging them in dense, ultra-large surface area, ultra-open-edge-length, self-organized and interconnected networks is demonstrated. The approach for the ultimate thickness reduction to 1–2 graphene layers is also proposed. The vertical graphene networks are optically transparent and show tunable electric properties from semiconducting to semi-metallic and metallic at room and near-room temperature, thus recovering semi-metallic properties of a single-layer graphene.

Control of morphology and electrical properties of self-organized graphenes in a plasma

The possibility of effective control of morphology and electrical properties of self-organized graphene structures on plasma-exposed Si surfaces is demonstrated. The structures are vertically standing nanosheets and can be grown without any catalyst and any external heating upon direct contact with high-density inductively coupled plasmas at surface temperatures not exceeding 673–723 K. Study of nucleation and growth dynamics revealed the possibility to switch-over between the two most common (turnstile- and maze-like) morphologies on the same substrates by a simple change of the plasma parameters. This change leads to the continuous or discontinuous native oxide layer that supports self-organized patterns of small carbon nanoparticles on which the structures nucleate. It is shown that by tailoring the nanoparticle arrangement one can create various three-dimensional architectures and networks of graphene nanosheet structures. We also demonstrate effective control of the degree of graphitization of the graphene nanosheet structures from the initial through the final growth stages. This makes it possible to tune the electrical resistivity properties of the produced three-dimensional patterns/networks from strongly dielectric to semiconducting. Our results contribute to enabling direct integration of graphene structures into presently dominant Si-based nanofabrication platform for next-generation nanoelectronic, sensor, biomedical, and optoelectronic components and nanodevices.

Structural, optical and electrical properties of Al-doped ZnO transparent conducting oxide for solar cell applications

Al-doped zinc oxide (AZO) thin films are deposited onto glass substrates using radio-frequency reactive magnetron sputtering and the improvements in their physical properties by post-synthesis thermal treatment are reported. X-ray diffraction spectra show that the structure of films can be controlled by adjusting the annealing temperatures, with the best crystallinity obtained at 400°C under a nitrogen atmosphere. These films exhibit improved quality and better optical transmittance as indicated by the UV-Vis spectra. Furthermore, the sheet resistivity is found to decrease from 1.87 × 10-3 to 5.63 × 10-4Ω⋅cm and the carrier mobility increases from 6.47 to 13.43 cm2 ⋅ V-1 ⋅ s-1 at the optimal annealing temperature. Our results demonstrate a simple yet effective way in controlling the structural, optical and electrical properties of AZO thin films, which is important for solar cell applications.

Synthesis, mechanical and electrical properties of carbon microcoils and nanocoils

The results on the synthesis, mechanical and electrical properties of carbon microcoils and nanocoils (CMCs, CNCs) synthesized using catalytic CVD and Ni-P and Co-P catalyst alloys, respectively, are reported. SEM analysis reveals that the CMCs and CNCs have unique helical morphologies, and diameters of 5.0-9.0 μm and 450-550 nm, respectively. Moreover, CMCs with flat cross-section can be stretched to 3 times their original coil lengths. Current-voltage characteristics of a single microcoil have also been obtained. It is found that the CMCs have the electrical conductivity between 100 and 160 S/cm, whereas the electrical resistance increases by about 20% during the coil extension. Besides, the microcoils can produce light in vacuum when the test voltage reaches 10 V. The emission intensity increases as the voltage increases. The mechanical and electrical properties of CMCs and CNC make them potentially useful in many applications in micromagnetic sensors, mechanical microsprings and optoelectronics.

Topological design and modulation strategy for buck-boost three-level inverters

To date, designed topologies for DC-AC inversion with both voltage-buck and boost capabilities are mainly focused on two-level circuitries with extensions to three-level possibilities left nearly unexplored. Contributing to this area of research, this paper presents the design of a number of viable buck-boost three-level inverters that can also support bidirectional power conversion. The proposed front-end circuitry is developed from the Cuk-derived buck-boost two-level inverter, and by using the "alternative phase opposition disposition" (APOD) modulation scheme, the buck-boost three-level inverters can perform distinct five-level line voltage and three-level phase voltage switching by simply controlling the active switches located in the designed voltage boost section of the circuits. As a cost saving option, one active switch can further be removed from the voltage-boost section of the circuits by simply re-routing the gating commands of the remaining switches without influencing the ac output voltage amplitude. To verify the validity of the proposed inverters, Matlab/PLECS simulations were performed before a laboratory prototype was implemented for experimental testing.

Topological design and modulation strategy for buck-boost three-level inverters

To date, designed topologies for DC-AC inversion with both voltage buck and boost capabilities are mainly focused on two-level circuitries with extensions to three-level possibilities left nearly unexplored. Contributing to this area of research, this paper presents the design of a number of viable buck-boost three-level inverters that can also support bidirectional power conversion. The proposed front-end circuitry is developed from the Cuk-derived buck-boost two-level inverter, and by using the ldquoalternative phase opposition dispositionrdquo modulation scheme, the buck-boost three-level inverters can perform distinct five-level line voltage and three-level phase voltage switching by simply controlling the active switches located in the designed voltage boost section of the circuits. As a cost saving option, one active switch can further be removed from the voltage boost section of the circuits by simply rerouting the gating commands of the remaining switches without influencing the AC output voltage amplitude. To verify the validity of the proposed inverters, MATLAB/PLECS simulations were performed before a laboratory prototype was implemented for experimental testing.

Performance evaluation of three-level Z-source inverters under semiconductor-failure conditions

This paper evaluates and proposes various compensation methods for three-level Z-source inverters under semiconductor-failure conditions. Unlike the fault-tolerant techniques used in traditional three-level inverters, where either an extra phase-leg or collective switching states are used, the proposed methods for three-level Z-source inverters simply reconfigure their relevant gating signals so as to ride-through the failed semiconductor conditions smoothly without any significant decrease in their ac-output quality and amplitude. These features are partly attributed to the inherent boost characteristics of a Z-source inverter, in addition to its usual voltage-buck operation. By focusing on specific types of three-level Z-source inverters, it can also be shown that, for the dual Z-source inverters, a unique feature accompanying it is its extra ability to force common-mode voltage to zero even under semiconductor-failure conditions. For verifying these described performance features, PLECS simulation and experimental testing were performed with some results captured and shown in a later section for visual confirmation.

Electrical insulation of high voltage inductor with co-axial electrode at floating voltage

Inductive fault current limiters (FCLs) have several advantages, such as significant current limitation, immediate triggering and relatively low losses. Despite these advantages, saturated core FCLs have not been commercialized due to its large size and associated high costs. A major remaining challenge is to reduce the footprint of the device. In this paper, a solution to reduce the overall footprint is proposed and discussed. In arrangements of windings on a core in reactors such as FCLs, the core is conventionally grounded. The electrical insulation distance between high voltage winding and core can be reduced if the core is left at floating potential. This paper shows the results of the investigation carried out on the insulation of such a coil-core assembly. Two experiments were conducted. In the first, the behavior of the apparatus under high voltage conditions was assessed by performing power frequency and lightning impulse tests. In the second experiment, a low voltage test was conducted during which voltages of different frequencies and pulses with varying rise times were applied. A finite element simulation was also carried out for comparison and further investigation

A high frequency, low voltage stackable full bridge module for modular multilevel cascade converter (MMCC) research

A new small full bridge module for MMCC research is presented. Each full bridge converter cell is a single small (65 × 30 mm) multilayer PCB with two low voltage high current (22 V, 40 A) integrated half bridge ICs and the necessary isolated control signals and auxiliary power supply (2500 V isolation). All devices are surface mount, minimising cell height (4 mm) and parasitic inductance. Each converter cell can be physically stacked with PCB connectors propagating the control signals and inter-cell power connections. Many cells can be trivially stacked to create a large multilevel converter leg with isolated auxiliary power and control signals. Any of the MMCC family members is then easily formed. With a change in placement of stacking connector, a parallel connection of bridges is also possible. Operation of a nine level parallel full bridge is demonstrated at 12 V and 384 kHz switching frequency delivering a 30 W 2 kHz sinewave into a resistive load. A number of new applications for this novel module aside from MMCC development are listed.

An improved gate driver for power MOSFETs using a cascode configuration

To overcome the limitations of existing gate drive topologies an improved gate drive concept is proposed to provide fast, controlled switching of power MOSFETs. The proposed topology exploits the cascode configuration with the inclusion of an active gate clamp to ensure that the driven MOSFET may be turned off under all load conditions. Key operating principles and advantages of the proposed gate drive topology are discussed. Characteristic waveforms are investigated via simulation and experimentation for the cascode driver in an inductive switching application at 375V and 10A. Experimental waveforms compared well with simulations with long gate charging delays (including the Miller plateau) being eliminated from the gate voltage waveform.

Doubly Fed Induction Generator for wind energy generation using nine-switch power converter

A Three-Phase Nine-Switch Converter (NSC) topology for Doubly Fed Induction Generator in wind energy generation is proposed in this paper. This converter topology was used in various applications such as Hybrid Electric Vehicles and Uninterruptable Power Supplies. In this paper, Nine-Switch Converter is introduced in Doubly Fed Induction Generator in renewable energy application for the first time. It replaces the conventional Back-to-Back Pulse Width Modulated voltage source converter (VSC) which composed of twelve switches in many DFIG applications. Reduction in number of switches is the most beneficial in terms of cost and power switching losses. The operation principle of Nine-Switch Converter using SPWM method is discussed. The resulting NSC performance of rotor side current control, active power and reactive control are compared with Back-to Back voltage source converter performance. DC link voltage regulation using front end converter is also presented. Finally the simulation results of DFIG performances using NSC and Back-to-Back VSC are analyzed and compared.

A high cell count cascade full bridge converter for wide bandwidth ultrasonic transducer excitation

A nine level modular multilevel cascade converter (MMCC) based on four full bridge cells is shown driving a piezoelectric ultrasonic transducer at 71 and 39 kHz, in simulation and experimentally. The modular cells are small stackable PCBs, each with two fully integrated surface mount 22 V, 40 A MOSFET half-bridge converters, and include all control signal and power isolation. In this work, the bridges operate at 12 V and 384 kHz, to deliver a 96 Vpp 9 level waveform with an effective switching frequency of 3 MHz. A 9 pH air cored inductor forms a low pass filter in conjunction with the 3000 pF capacitance of the transducer load. Eight equally phase-displaced naturally sampled pulse width modulation (PWM) drive signals, along with the modulating sinusoid, are generated using phase accumulation techniques in a dedicated FPGA. Experimental time domain and FFT plots of the multilevel and transducer output waveforms are presented and discussed.