49 resultados para Desenho interfaces gráficas


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The growth of APIs and Web services on the Internet, especially through larger enterprise systems increasingly being leveraged for Cloud and software-as-a-service opportuni- ties, poses challenges to improving the efficiency of integration with these services. Interfaces of enterprise systems are typically larger, more complex and overloaded, with single operation having multiple data entities and parameter sets, supporting varying requests, and reflecting versioning across different system releases, compared to fine-grained operations of contemporary interfaces. We propose a technique to support the refactoring of service interfaces by deriving business entities and their relationships. In this paper, we focus on the behavioural aspects of service interfaces, aiming to discover the sequential dependencies of operations (otherwise known as protocol extraction) based on the entities and relationships derived. Specifically, we propose heuristics according to these relationships, and in turn, deriving permissible orders in which operations are invoked. As a result of this, service operations can be refactored on business entity CRUD lines, with explicit behavioural protocols as part of an interface definition. This supports flexible service discovery, composition and integration. A prototypical implementation and analysis of existing Web services, including those of commercial logistic systems (Fedex), are used to validate the algorithms proposed through the paper.

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We describe the design of a digital noticeboard to support communication within a remote Aboriginal community whose aspiration is to live in "both worlds", nurturing and extending their Aboriginal culture and actively participating in Western society and economy. Three bi-cultural aspects have emerged and are presented here: the need for a bi-lingual noticeboard to span both oral and written language traditions, the tension between perfunctory information exchange and social, embodied protocols of telling in person and the different ways in which time is represented in both cultures. The design approach, developed iteratively through consultation, demonstration and testing led to an "unsurprising interface", aimed at maximizing use and appropriation across cultures by unifying visual, text and spoken contents in both passive and interactive displays in a modeless manner.

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Natural User Interfaces (NUI) offer rich ways for interacting with the digital world that make innovative use of existing human capabilities. They include and often combine different input modalities such as voice, gesture, eye gaze, body interactions, touch and touchless interactions. However much of the focus of NUI research and development has been on enhancing the experience of individuals interacting with technology. Effective NUIs must also acknowledge our innately social characteristics, and support how we communicate with each other, play together, learn together and collaboratively work together. This workshop concerns the social aspects of NUI. The workshop seeks to better understand the social uses and applications of these new NUI technologies -- how we design these technologies for new social practices and how we understand the use of these technologies in key social contexts.

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Network Interfaces (NIs) are used in Multiprocessor System-on-Chips (MPSoCs) to connect CPUs to a packet switched Network-on-Chip. In this work we introduce a new NI architecture for our hierarchical CoreVA-MPSoC. The CoreVA-MPSoC targets streaming applications in embedded systems. The main contribution of this paper is a system-level analysis of different NI configurations, considering both software and hardware costs for NoC communication. Different configurations of the NI are compared using a benchmark suite of 10 streaming applications. The best performing NI configuration shows an average speedup of 20 for a CoreVA-MPSoC with 32 CPUs compared to a single CPU. Furthermore, we present physical implementation results using a 28 nm FD-SOI standard cell technology. A hierarchical MPSoC with 8 CPU clusters and 4 CPUs in each cluster running at 800MHz requires an area of 4.56mm2.