7 resultados para instructional roadmap

em Indian Institute of Science - Bangalore - Índia


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A tactical gaming model for wargame play between two teams A and B through a control unit C has been developed, which can be handled using IBM personal computers (XT and AT models) having a local area network facility. This simulation model involves communication between the teams involved, logging and validation of the actions of the teams by the control unit. The validation procedure uses statistical and also monte carlo techniques. This model has been developed to evaluate the planning strategies of the teams involved. This application software using about 120 files has been developed in BASIC, DBASE and the associated network software. Experience gained in the instruction courses using this model will also be discussed.

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The worldwide research in nanoelectronics is motivated by the fact that scaling of MOSFETs by conventional top down approach will not continue for ever due to fundamental limits imposed by physics even if it is delayed for some more years. The research community in this domain has largely become multidisciplinary trying to discover novel transistor structures built with novel materials so that semiconductor industry can continue to follow its projected roadmap. However, setting up and running a nanoelectronics facility for research is hugely expensive. Therefore it is a common model to setup a central networked facility that can be shared with large number of users across the research community. The Centres for Excellence in Nanoelectronics (CEN) at Indian Institute of Science, Bangalore (IISc) and Indian Institute of Technology, Bombay (IITB) are such central networked facilities setup with funding of about USD 20 million from the Department of Information Technology (DIT), Ministry of Communications and Information Technology (MCIT), Government of India, in 2005. Indian Nanoelectronics Users Program (INUP) is a missionary program not only to spread awareness and provide training in nanoelectronics but also to provide easy access to the latest facilities at CEN in IISc and at IITB for the wider nanoelectronics research community in India. This program, also funded by MCIT, aims to train researchers by conducting workshops, hands-on training programs, and providing access to CEN facilities. This is a unique program aiming to expedite nanoelectronics research in the country, as the funding for projects required for projects proposed by researchers from around India has prior financial approval from the government and requires only technical approval by the IISc/ IITB team. This paper discusses the objectives of INUP, gives brief descriptions of CEN facilities, the training programs conducted by INUP and list various research activities currently under way in the program.

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Sampling based planners have been successful in path planning of robots with many degrees of freedom, but still remains ineffective when the configuration space has a narrow passage. We present a new technique based on a random walk strategy to generate samples in narrow regions quickly, thus improving efficiency of Probabilistic Roadmap Planners. The algorithm substantially reduces instances of collision checking and thereby decreases computational time. The method is powerful even for cases where the structure of the narrow passage is not known, thus giving significant improvement over other known methods.

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In this study, the potential for increasing the tree cover and thereby the biomass and carbon as a mitigation option of three categories of wastelands, irrespective of their tenure, are considered. The area under wastelands in Himachal Pradesh, according to NRSA (2005), is estimated to be 2.83 Mha. Among the 28 categories of wastelands reported by NRSA, only 15 categories exist in Himachal Pradesh. In the present study, three land categories are considered for estimating the mitigation potential. They include: (i) Degraded forestland, (ii) Degraded community land and (iii) Degraded and abandoned private land. Choice of species or the mix of species to be planted on the three land categories considered for reforestation is discussed. Carbon pools considered in the present study are those, which account only for aboveground biomass, belowground biomass and soil organic carbon. This study estimates the mitigation potential at the state level considering land available under more than one category. It also provides a roadmap for future work in support of mitigation analysis and implementation.

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With the rapid scaling down of the semiconductor process technology, the process variation aware circuit design has become essential today. Several statistical models have been proposed to deal with the process variation. We propose an accurate BSIM model for handling variability in 45nm CMOS technology. The MOSFET is designed to meet the specification of low standby power technology of International Technology Roadmap for Semiconductors (ITRS).The process parameters variation of annealing temperature, oxide thickness, halo dose and title angle of halo implant are considered for the model development. One parameter variation at a time is considered for developing the model. The model validation is done by performance matching with device simulation results and reported error is less than 10%.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

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In recent years, there has been an upsurge of research interest in cooperative wireless communications in both academia and industry. This article presents a simple overview of the pivotal topics in both mobile station (MS)- and base station (BS)- assisted cooperation in the context of cellular radio systems. Owing to the ever-increasing amount of literature in this particular field, this article is by no means exhaustive, but is intended to serve as a roadmap by assembling a representative sample of recent results and to stimulate further research. The emphasis is initially on relay-base cooperation, relying on network coding, followed by the design of cross-layer cooperative protocols conceived for MS cooperation and the concept of coalition network element (CNE)-assisted BS cooperation. Then, a range of complexity and backhaul traffic reduction techniques that have been proposed for BS cooperation are reviewed. A more detailed discussion is provided in the context of MS cooperation concerning the pros and cons of dispensing with high-complexity, power-hungry channel estimation. Finally, generalized design guidelines, conceived for cooperative wireless communications, are presented.

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While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.