128 resultados para Unbalanced circuit

em Indian Institute of Science - Bangalore - Índia


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This paper presents an Artificial Neural Network (ANN) approach for locating faults in distribution systems. Different from the traditional Fault Section Estimation methods, the proposed approach uses only limited measurements. Faults are located according to the impedances of their path using a Feed Forward Neural Networks (FFNN). Various practical situations in distribution systems, such as protective devices placed only at the substation, limited measurements available, various types of faults viz., three-phase, line (a, b, c) to ground, line to line (a-b, b-c, c-a) and line to line to ground (a-b-g, b-c-g, c-a-g) faults and a wide range of varying short circuit levels at substation, are considered for studies. A typical IEEE 34 bus practical distribution system with unbalanced loads and with three- and single- phase laterals and a 69 node test feeder with different configurations are considered for studies. The results presented show that the proposed approach of fault location gives close to accurate results in terms of the estimated fault location.

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A simple equivalent circuit model for the analysis of dispersion and interaction impedance characteristics of serpentine folded-waveguide slow-wave structure was developed by considering the straight and curved portions of structure supporting the dominant TE10-mode of the rectangular waveguide. Expressions for the lumped capacitance and inductance per period of the slow-wave structure were derived in terms of the physical dimensions of the structure, incorporating the effects of the beam-hole in the lumped parameters. The lumped parameters were subsequently interpreted for obtaining the dispersion and interaction impedance characteristics of the structure. The analysis was simple yet accurate in predicting the dispersion and interaction impedance behaviour at millimeter-wave frequencies. The analysis was benchmarked against measurement as well as with 3D electromagnetic modeling using MAFIA for two typical slow-wave structures (one at the Ka-band and the other at the W-band) and close agreement observed.

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An inexpensive and simple circuit to aid the direct measurement of majority carrier capture cross sections of impurity levels in the band gap of a semiconductor by the variable width filling pulse technique is presented. With proper synchronisation, during the period of application of the pulse, the device is disconnected from the capacitance meter to avoid distortion of the pulse and is reconnected again to the meter to record the emission transient. Modes of operation include manual triggering for long emission transients, repetitive triggering for isothermal and DLTS measurements and the DLTS mode which is to be used with signal analysers that already provide a synchronising pulse for disconnection.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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The operation of thyristor-controlled static VAR compensators (SVCs) at various conduction angles can be used advantageously to meet the unablanced reactive power demands in a system. However, such operation introduces harmonic currents into the AC system. This paper presents an algorithm to evaluate an optimum combination of the phase-wise reactive power generations from SVC and balanced reactive power supply from the AC system, based on the defined performance indices, namely, the telephone influence factor (TIF), the total harmonic current factor (IT) and the distortion factor (D). Results of the studies conducted on a typical distribution system are presented and discussed.

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A simple linear ramp control circuit, suitable for use with force-commutated thyrister circuits is discussed here. The circuit is based on only two IM 558 dual timer iCs, operating from a single 15 V supply. The reset terminals facilitate inhibition of the output of any stage. The use of this circuit in a thyristor chopper operating at 400 Hz 13 described.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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On interrupting polarisation, the magnesium anode exhibits a negative overshoot in potential followed by a slow recovery to a steady state value. A model has been proposed to explain the opencircuit potential-time transient in terms of a spontaneous passivation of the metal and the consequent changes in the corrosion potential. Theoretical expressions have been derived for the timedependence of the open-circuit electrode potential. Calculated, potential-time curves thus obtained are in qualitative agreement with experimental data. A possible application of this phenomenon to develop non-destructive quality control tests of Mg, Li and Al-based dry cells has been pointed out.

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The Printed Circuit Board (PCB) layout design is one of the most important and time consuming phases during equipment design process in all electronic industries. This paper is concerned with the development and implementation of a computer aided PCB design package. A set of programs which operate on a description of the circuit supplied by the user in the form of a data file and subsequently design the layout of a double-sided PCB has been developed. The algorithms used for the design of the PCB optimise the board area and the length of copper tracks used for the interconnections. The output of the package is the layout drawing of the PCB, drawn on a CALCOMP hard copy plotter and a Tektronix 4012 storage graphics display terminal. The routing density (the board area required for one component) achieved by this package is typically 0.8 sq. inch per IC. The package is implemented on a DEC 1090 system in Pascal and FORTRAN and SIGN(1) graphics package is used for display generation.

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The recent trend towards minimizing the interconnections in large scale integration (LSI) circuits has led to intensive investigation in the development of ternary circuits and the improvement of their design. The ternary multiplexer is a convenient and useful logic module which can be used as a basic building block in the design of a ternary system. This paper discusses a systematic procedure for the simplification and realization of ternary functions using ternary multiplexers as building blocks. Both single level and multilevel multiplexing techniques are considered. The importance of the design procedure is highlighted by considering two specific applications, namely, the development of ternary adder/subtractor and TCD to ternary converter.

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Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current which results into supply, voltage droop and eventually yield loss. This paper proposes an efficient methodology for test vector re-ordering to achieve minimum peak power supported by the given test vector set. The proposed methodology also minimizes average power under the minimum peak power constraint. A methodology to further reduce the peak power below the minimum supported peak power, by inclusion of minimum additional vectors is also discussed. The paper defines the lower bound on peak power for a given test set. The results on several benchmarks shows that it can reduce peak power by up to 27%.

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An isolated wind power generation scheme using slip ring induction machine (SRIM) is proposed. The proposed scheme maintains constant load voltage and frequency irrespective of the wind speed or load variation. The power circuit consists of two back-to-back connected inverters with a common dc link, where one inverter is directly connected to the rotor side of SRIM and the other inverter is connected to the stator side of the SRIM through LC filter. Developing a negative sequence compensation method to ensure that, even under the presence of unbalanced load, the generator experiences almost balanced three-phase current and most of the unbalanced current is directed through the stator side converter is the focus here. The SRIM controller varies the speed of the generator with variation in the wind speed to extract maximum power. The difference of the generated power and the load power is either stored in or extracted from a battery bank, which is interfaced to the common dc link through a multiphase bidirectional fly-back dc-dc converter. The SRIM control scheme, maximum power point extraction algorithm and the fly-back converter topology are incorporated from available literature. The proposed scheme is both simulated and experimentally verified.

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This paper proposes a control method that can balance the input currents of the three-phase three-wire boost rectifier under unbalanced input voltage condition. The control objective is to operate the rectifier in the high-power-factor mode under balanced input voltage condition but to give overriding priority to the current balance function in case of unbalance in the input voltage. The control structure has been divided into two major functional blocks. The inner loop current-mode controller implements resistor emulation to achieve high-power-factor operation on each of the two orthogonal axes of the stationary reference frame. The outer control loop performs magnitude scaling and phase-shifting operations on current of one of the axes to make it balanced with the current on the other axis. The coefficients of scaling and shifting functions are determined by two closed-loop prportional-integral (PI) controllers that impose the conditions of input current balance as PI references. The control algorithm is simple and high performing. It does not require input voltage sensing and transformation of the control variables into a rotating reference frame. The simulation results on a MATLAB-SIMULINK platform validate the proposed control strategy. In implementation Texas Instrument's digital signal processor TMS320F24OF is used as the digital controller. The control algorithm for high-power-factor operation is tested on a prototype boost rectifier under nominal and unbalanced input voltage conditions.

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A new solution for unbalanced and nonlinear loads in terms of power circuit topology and controller structure is proposed in this paper. A three-phase four-wire high-frequency ac-link inverter is adopted to cater to such loads. Use of high-frequency transformer results in compact and light-weight systems. The fourth wire is taken out from the midpoint of the isolation transformer in order to avoid the necessity of an extra leg. This makes the converter suitable for unbalanced loads and eliminates the requirements of bulky capacitor in half-bridge inverter. The closed-loop control is carried out in stationary reference frame using proportional + multiresonant controller (three separate resonant controller for fundamental, fifth and seventh harmonic components). The limitations on improving steady-state response of harmonic resonance controllers is investigated and mitigated using a lead-lag compensator. The proposed voltage controller is used along with an inner current loop to ensure excellent performance of the power converter. Simulation studies and experimental results with 1 kVA prototype under nonlinear and unbalanced loading conditions validate the proposed scheme.