Optimization of HfO2 films for high transconductance back gated graphene transistors

Hafnium dioxide (HfO2) films, deposited using electron beam evaporation, are optimized for high performance back-gated graphene transistors. Bilayer graphene is identified on HfO2/Si substrate using optical microscope and subsequently confirmed with Raman spectroscopy. Back-gated graphene transistor, with 32 nm thick HfO2 gate dielectric, has been fabricated with very high transconductance value of 60 mu S. From the hysteresis of the current-voltage characteristics, we estimate the trap density in HfO2 to be in the mid 10(11)/cm(2) range, comparable to SiO2.

Justifying threshold voltage definition for undoped body transistors through ``crossover point'' concept

Two different definitions, one is potential based and the other is charge based, are used in the literatures to define the threshold voltage of undoped body symmetric double gate transistors. This paper, by introducing a novel concept of crossover point, proves that the charge based definition is more accurate than the potential based definition. It is shown that for a given channel length the potential based definition predicts anomalous change in threshold voltage with body thickness variation while the charge based definition results in monotonous change. The threshold voltage is then extracted from drain current versus gate voltage characteristics using linear extrapolation, transconductance and match-point methods. In all the three cases it is found that trend of threshold voltage variation support the charge based definition.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.

Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET

In this paper we show the effect of electron-phonon scattering on the performance of monolayer (1L) MoS2 and WSe2 channel based n-MOSFETs. Electronic properties of the channel materials are evaluated using the local density approximation (LDA) in density functional theory (DFT). For phonon dispersion we employ the small displacement / frozen phonon calculations in DFT. Thereafter using the non-equilibrium Green's function (NEGF) formalism, we study the effect of electron-phonon scattering and the contribution of various phonon modes on the performance of such devices. It is found that the performance of the WSe2 device is less impacted by phonon scattering, showing a ballisticity of 83% for 1L-WSe2 FET for channel length of 10 nm. Though 1L-MoS2 FET of similar dimension shows a lesser ballisticity of 75%. Also in the presence of scattering there exist a a 21-36% increase in the intrinsic delay time (tau) and a 10-18% reduction in peak transconductance (g(m)) for WSe2 and MoS2 devices respectively. (C) 2015 Author(s).

Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.

Design Optimization of Thin-Film Transistors Based on a Metal-Substrate-Semiconductor Architecture for High DC Voltage Sensing

We discuss the potential application of high dc voltage sensing using thin-film transistors (TFTs) on flexible substrates. High voltage sensing has potential applications for power transmission instrumentation. For this, we consider a gate metal-substrate-semiconductor architecture for TFTs. In this architecture, the flexible substrate not only provides mechanical support but also plays the role of the gate dielectric of the TFT. Hence, the thickness of the substrate needs to be optimized for maximizing transconductance, minimizing mechanical stress, and minimizing gate leakage currents. We discuss this optimization, and develop n-type and p-type organic TFTs using polyvinyldene fluoride as the substrate-gate insulator. Circuits are also realized to achieve level shifting, amplification, and high drain voltage operation.