17 resultados para Trade-Marks

em Indian Institute of Science - Bangalore - Índia


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Surface texture influences friction and transfer layer formation during sliding. In the present investigation, basic studies were conducted using inclined pin-on-plate sliding tester to understand the effect of directionality of surface grinding marks of hard material on friction and transfer layer formation during sliding against soft materials. 080 M40 steel plates were ground to attain different surface roughness with unidirectional grinding marks. Then pins made of soft materials such as pure Al, pure Mg and Al-Mg alloy were slid against the prepared steel plates. Grinding angle (i.e., the angle between direction of sliding and grinding marks) was varied between 0 degrees and 90 degrees in the tests. Experiments were conducted under both dry and lubricated conditions on each plate in ambient environment. It was observed that the transfer layer formation and the coefficient of friction, which has two components adhesion and plowing - depend primarily on the directionality of grinding marks of the harder mating surface, and independent of surface roughness of the harder mating surface. For the case of pure Mg, stick-slip phenomenon was observed under dry condition for all grinding angles and it was absent upto 20 degrees grinding angles under lubricated condition. However, for the case of Al, it was observed only under lubricated conditions for angles exceeding 20 degrees. As regards the alloy, namely, Al-Mg alloy, it, was absent in both conditions. For the case of pure Mg and Al, it was observed that the amplitude of stick-slip motion primarily depends on plowing component of friction. The grinding angle effect on coefficient of friction was attributed to the variation of plowing component of friction with grinding angle.

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This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

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Abstract is not available.

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Background: Protein kinases are involved in diverse spectrum of cellular processes. Availability of draft version of the human genomic data in the year 2001 enabled recognition of repertoire of protein kinases. However, over the years the human genomic data is being refined and the current release of human genomic data has helped us to recognize a larger repertoire of over 900 human protein kinases represented mainly by splice variants. Results: Many of these identified protein kinases are alternatively spliced products. Interestingly, some of the human kinase splice variants appear to be significantly diverged in terms of their functional properties as represented by incorporation or absence of one or more domains. Many sets of protein kinase splice variants have substantially different domain organization and in a few sets of splice variants kinase domains belong to different subfamilies of kinases suggesting potential participation in different signal transduction pathways. Conclusions: Addition or deletion of a domain between splice variants of multi-domain kinases appears to be a means of generating differences in the functional features of otherwise similar kinases. It is intriguing that marked sequence diversity within the catalytic regions of some of the splice variant kinases result in kinases belonging to different subfamilies. These human kinase splice variants with different functions might contribute to diversity of eukaryotic cellular signaling.

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Surface topography has been known to play an important role in the friction and transfer layer formation during sliding. In the present investigation, EN8 steel flats were ground to attain different surface roughness with unidirectional grinding marks. Pure Mg pins were scratched on these surfaces using an Inclined Scratch Tester to study the influence of directionality of surface grinding marks on coefficient of friction and transfer layer formation. Grinding angle (i.e., the angle between direction of scratch and grinding marks) was varied between 0 degrees and 90 degrees during the tests. Experiments were conducted under both dry and lubricated conditions. Scanning electron micrographs of the contact surfaces of pins and flats were used to reveal the surface features that included the morphology of the transfer layer. It was observed that the average coefficient of friction and transfer layer formation depend primarily on the directionality of the grinding marks but were independent of surface roughness on the harder mating surface. In addition, a stick-slip phenomenon was observed, the amplitude of which depended both on the directionality of grinding marks and the surface roughness of the harder mating surface. The grinding angle effect on the coefficient of friction, which consists of adhesion and plowing components, was attributed to the variation of plowing component of friction. (c) 2006 Elsevier B.V. All rights reserved.

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Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

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A common and practical paradigm in cooperative communication systems is the use of a dynamically selected `best' relay to decode and forward information from a source to a destination. Such systems use two phases - a relay selection phase, in which the system uses transmission time and energy to select the best relay, and a data transmission phase, in which it uses the spatial diversity benefits of selection to transmit data. In this paper, we derive closed-form expressions for the overall throughput and energy consumption, and study the time and energy trade-off between the selection and data transmission phases. To this end, we analyze a baseline non-adaptive system and several adaptive systems that adapt the selection phase, relay transmission power, or transmission time. Our results show that while selection yields significant benefits, the selection phase's time and energy overhead can be significant. In fact, at the optimal point, the selection can be far from perfect, and depends on the number of relays and the mode of adaptation. The results also provide guidelines about the optimal system operating point for different modes of adaptation. The analysis also sheds new insights on the fast splitting-based algorithm considered in this paper for relay selection.

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We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

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Electronic exchanges are double-sided marketplaces that allow multiple buyers to trade with multiple sellers, with aggregation of demand and supply across the bids to maximize the revenue in the market. Two important issues in the design of exchanges are (1) trade determination (determining the number of goods traded between any buyer-seller pair) and (2) pricing. In this paper we address the trade determination issue for one-shot, multi-attribute exchanges that trade multiple units of the same good. The bids are configurable with separable additive price functions over the attributes and each function is continuous and piecewise linear. We model trade determination as mixed integer programming problems for different possible bid structures and show that even in two-attribute exchanges, trade determination is NP-hard for certain bid structures. We also make some observations on the pricing issues that are closely related to the mixed integer formulations.

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The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

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We consider a complex, additive, white Gaussian noise channel with flat fading. We study its diversity order vs transmission rate for some known power allocation schemes. The capacity region is divided into three regions. For one power allocation scheme, the diversity order is exponential throughout the capacity region. For selective channel inversion (SCI) scheme, the diversity order is exponential in low and high rate region but polynomial in mid rate region. For fast fading case we also provide a new upper bound on block error probability and a power allocation scheme that minimizes it. The diversity order behaviour of this scheme is same as for SCI but provides lower BER than the other policies.

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In recent times, crowdsourcing over social networks has emerged as an active tool for complex task execution. In this paper, we address the problem faced by a planner to incen-tivize agents in the network to execute a task and also help in recruiting other agents for this purpose. We study this mecha-nism design problem under two natural resource optimization settings: (1) cost critical tasks, where the planner’s goal is to minimize the total cost, and (2) time critical tasks, where the goal is to minimize the total time elapsed before the task is executed. We define a set of fairness properties that should beideally satisfied by a crowdsourcing mechanism. We prove that no mechanism can satisfy all these properties simultane-ously. We relax some of these properties and define their ap-proximate counterparts. Under appropriate approximate fair-ness criteria, we obtain a non-trivial family of payment mech-anisms. Moreover, we provide precise characterizations of cost critical and time critical mechanisms.

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In this paper, the storage-repair-bandwidth (SRB) trade-off curve of regenerating codes is reformulated to yield a tradeoff between two global parameters of practical relevance, namely information rate and repair rate. The new information-repair-rate (IRR) tradeoff provides a different and insightful perspective on regenerating codes. For example, it provides a new motivation for seeking to investigate constructions corresponding to the interior of the SRB tradeoff. Interestingly, each point on the SRB tradeoff corresponds to a curve in the IRR tradeoff setup. We characterize completely, functional repair under the IRR framework, while for exact repair, an achievable region is presented. In the second part of this paper, a rate-half regenerating code for the minimum storage regenerating point is constructed that draws upon the theory of invariant subspaces. While the parameters of this rate-half code are the same as those of the MISER code, the construction itself is quite different.

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The agriculture, forestry and other land use (AFOLU) sector is responsible for approximately 25% of anthropogenic GHG emissions mainly from deforestation and agricultural emissions from livestock, soil and nutrient management. Mitigation from the sector is thus extremely important in meeting emission reduction targets. The sector offers a variety of cost-competitive mitigation options with most analyses indicating a decline in emissions largely due to decreasing deforestation rates. Sustainability criteria are needed to guide development and implementation of AFOLU mitigation measures with particular focus on multifunctional systems that allow the delivery of multiple services from land. It is striking that almost all of the positive and negative impacts, opportunities and barriers are context specific, precluding generic statements about which AFOLU mitigation measures have the greatest promise at a global scale. This finding underlines the importance of considering each mitigation strategy on a case-by-case basis, systemic effects when implementing mitigation options on the national scale, and suggests that policies need to be flexible enough to allow such assessments. National and international agricultural and forest (climate) policies have the potential to alter the opportunity costs of specific land uses in ways that increase opportunities or barriers for attaining climate change mitigation goals. Policies governing practices in agriculture and in forest conservation and management need to account for both effective mitigation and adaptation and can help to orient practices in agriculture and in forestry towards global sharing of innovative technologies for the efficient use of land resources. Different policy instruments, especially economic incentives and regulatory approaches, are currently being applied however, for its successful implementation it is critical to understand how land-use decisions are made and how new social, political and economic forces in the future will influence this process.