Static RAM cell for ternary logic

A novel CMOS static RAM cell for ternary logic systems is described. This cell is based on the lambda diode. The operation of the cell has been simulated using the SPICE 2G program. The results of the simulation are given.

Ternary function and circuit design using ternary multiplexers

The recent trend towards minimizing the interconnections in large scale integration (LSI) circuits has led to intensive investigation in the development of ternary circuits and the improvement of their design. The ternary multiplexer is a convenient and useful logic module which can be used as a basic building block in the design of a ternary system. This paper discusses a systematic procedure for the simplification and realization of ternary functions using ternary multiplexers as building blocks. Both single level and multilevel multiplexing techniques are considered. The importance of the design procedure is highlighted by considering two specific applications, namely, the development of ternary adder/subtractor and TCD to ternary converter.

Synthesis, structure and properties elf a new ternary interstitial nitride: Ni2W3N

A new ternary interstitial nitride Ni2W3N has been synthesized by the ammonolysis of different oxide precursors and characterized by powder X-ray diffraction and electron microscopy. This nitride crystallizes in the cubic space group P4(1)32(213) [Ni2W3N, a=6.663(1) Angstrom, Z=4] and is isostructural with Al2Mo3C. This compound belongs to the rare class of intermetallic ternary nitrides and carbides crystallizing with a filled beta-Mn structure. Ni2W3N is not stable, it decomposes to a new compound NiW3N related to the distorted anti-perovskite, Ca3AsN structure.

Photoinduced DNA and Protein Cleavage Activity of Ferrocene-Conjugated Ternary Copper(II) Complexes

Ferrocene-conjugated ternary copper(II) complexes [Cu(L)(B)](ClO4)(2), where L is FcCH(2)N(CH2Py)(2) (Fc = (eta(5)-C5H4)Fe-II(eta(5)-C5H5)) and B is a phenanthroline base, viz., 2,2'-bipyridine (bpy, 1), 1, 10-phenanthroline (phen, 2), dipyrido[3,2-d:2',3'-f]quinoxaline (dpq, 3), and dipyrido[3,2-a:2',3'-c]phenazine (dppz, 4), have been synthesized and characterized by various spectroscopic and analytical techniques. The bpy complex 1, as its hexafluorophosphate salt, has been structurally characterized by X-ray crystallography. The molecular structure shows the copper(II) center having an essentially square-pyramidal coordination geometry in which L with a pendant ferrocenyl (Fc) moiety and bpy show respective tridentate and bidentate modes of binding to the metal center. The complexes are redox active, showing a reversible cyclic voltammetric response of the Fc(+)-Fc couple near 0.5 V vs SCE and a quasi-reversible Cu(II)-Cu(I) couple near 0.0 V. Complexes 2-4 show binding affinity to calf thymus (CT) DNA, giving binding constant (K-b) values in the range of 4.2 x 10(4) to 2.5 x 10(5) M-1. Thermal denaturation and viscometric titration data suggest groove binding and/or a partial intercalative mode of binding of the complexes to CT DNA. The complexes show good binding propensity to the bovine serum albumin (BSA) protein, giving K-BSA values of similar to 10(4) M-1 for the bpy and phen complexes and similar to 10(5) M-1 for the dpq and dppz complexes. Complexes 2-4 exhibit efficient chemical nuclease activity in the presence of 3-mercapto-propionic acid (MPA) as a reducing agent or hydrogen peroxide (H2O2) as an oxidizing agent. Mechanistic studies reveal formation of hydroxyl radicals as the reactive species. The dpq and dppz complexes are active in cleaving supercoiled (SC) pUC19 DNA on photoexposure to visible light of different wavelengths including red light using an argon-krypton mixed gas ion laser. Mechanistic investigations using various inhibitors reveal the fort-nation of hydroxyl radicals in the DNA photocleavage reactions. The dppz complex 4, which shows efficient photoioduced BSA cleavage activity, is a potent multifunctional model nuclease and protease in the chemistry of photodynamic therapy (PDT) of cancer.

Glass forming ability and stability: Ternary Cu bearing Ti, Zr, Hf alloys

Four Cu bearing alloys of nominal composition Zr25Ti25Cu50, Zr34Ti16Cu50, Zr25Hf25Cu50 and Ti25Hf25Cu50 have been rapidly solidified in order to produce ribbons. All the alloys become amorphous after meltspinning. In the Zr34Ti16Cu50 alloy localized precipitation of cF24 Cu5Zr phase can be observed in the amorphous matrix. The alloys show a tendency of phase separation at the initial stages of crystallization. The difference in crystallization behavior of these alloys with Ni bearing ternary alloys can be explained by atomic size, binary heat of mixing and Mendeleev number. It has been observed that both Laves and Anti-Laves phase forming compositions are suitable for glass formation. The structures of the phases, precipitated during rapid solidification and crystallization can be viewed in terms of Bernal deltahedra and Frank-Kasper polyhedra.

Fuzzy Logic-Based Approaches in Water Resource System Modelling

Recent research in modelling uncertainty in water resource systems has highlighted the use of fuzzy logic-based approaches. A number of research contributions exist in the literature that deal with uncertainty in water resource systems including fuzziness, subjectivity, imprecision and lack of adequate data. This chapter presents a broad overview of the fuzzy logic-based approaches adopted in addressing uncertainty in water resource systems modelling. Applications of fuzzy rule-based systems and fuzzy optimisation are then discussed. Perspectives on the scope for further research are presented.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

A study of placement algorithms through trial interchange of logic modules

Based on trial interchanges, this paper develops three algorithms for the solution of the placement problem of logic modules in a circuit. A significant decrease in the computation time of such placement algorithms can be achieved by restricting the trial interchanges to only a subset of all the modules in a circuit. The three algorithms are simulated on a DEC 1090 system in Pascal and the performance of these algorithms in terms of total wirelength and computation time is compared with the results obtained by Steinberg, for the 34-module backboard wiring problem. Performance analysis of the first two algorithms reveals that algorithms based on pairwise trial interchanges (2 interchanges) achieve a desired placement faster than the algorithms based on trial N interchanges. The first two algorithms do not perform better than Steinberg's algorithm1, whereas the third algorithm based on trial pairwise interchange among unconnected pairs of modules (UPM) and connected pairs of modules (CPM) performs better than Steinberg's algorithm, both in terms of total wirelength (TWL) and computation time.

A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays

In this paper, the validity of'single fault assumption in deriving diagnostic test sets is examined with respect to crosspoint faults in programmable logic arrays (PLA's). The control input procedure developed here can be used to convert PLA's having undetectable crosspoint faults to crosspoint-irredundant PLA's for testing purposes. All crosspoints will be testable in crosspoint-irredundant PLA's. The control inputs are used as extra variables during testing. They are maintained at logic I during normal operation. A useful heuristic for obtaining a near-minimal number of control inputs is suggested. Expressions for calculating bounds on the number of control inputs have also been obtained.

An on-line algorithm for the location of cross point faults in programmable logic arrays

An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.

A ternary Schmitt trigger

A new ternary circuit, namely, a ternary Schmitt trigger, is presented. This novel circuit which is based on the well-known lambda diode, is suitable for integration using CMOS technology. The circuit has been simulated using the SPICE 2G Program. The results of the simulation are presented. The circuit offers a high degree of design flexibility. This circuit is expected to be a very useful functional block in the processing of ternary and pseudoternary signals.

A fuzzy logic based dynamic wave model inversion algorithm for canal regulation

A fuzzy logic based centralized control algorithm for irrigation canals is presented. Purpose of the algorithm is to control downstream discharge and water level of pools in the canal, by adjusting discharge release from the upstream end and gates settings. The algorithm is based on the dynamic wave model (Saint-Venant equations) inversion in space, wherein the momentum equation is replaced by a fuzzy rule based model, while retaining the continuity equation in its complete form. The fuzzy rule based model is developed on fuzzification of a new mathematical model for wave velocity, the derivational details of which are given. The advantages of the fuzzy control algorithm, over other conventional control algorithms, are described. It is transparent and intuitive, and no linearizations of the governing equations are involved. Timing of the algorithm and method of computation are explained. It is shown that the tuning is easy and the computations are straightforward. The algorithm provides stable, realistic and robust outputs. The disadvantage of the algorithm is reduced precision in its outputs due to the approximation inherent in the fuzzy logic. Feed back control logic is adopted to eliminate error caused by the system disturbances as well as error caused by the reduced precision in the outputs. The algorithm is tested by applying it to water level control problem in a fictitious canal with a single pool and also in a real canal with a series of pools. It is found that results obtained from the algorithm are comparable to those obtained from conventional control algorithms.

Energetics of the condensed ternary fuel-oxidizer systems

the heats of reaction of an oxygen-balanced ternary fuel-oxidizer system have been shown to be linearly related to the total oxidizing valences (P0) of the composition. Because calculation of P0 is simple, the method is found to help in evaluating the energetics of such systems. The accuracy of the method when applied to various ternary systems has been discussed.

An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays

An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the valgorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.