Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.

Energy-efficient redundant execution for chip multiprocessors

Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chip fault tolerance in future chip microprocessors (CMPs). In this paper, we describe a power-efficient architecture for redundant execution on chip multiprocessors (CMPs) which when coupled with our per-core dynamic voltage and frequency scaling (DVFS) algorithm significantly reduces the energy overhead of redundant execution without sacrificing performance. Our evaluation shows that this architecture has a performance overhead of only 0.3% and consumes only 1.48 times the energy of a non-fault-tolerant baseline.