SOCS3 expression induced by PIM2 requires PKC and PI3K signaling

Initiation of proinflammatory host immunity in response to infection represents as a key event in effective control and containment of the pathogen at the site of infection as well as in elicitation of robust immune memory responses. In the current investigation, we demonstrate that an integral cell wall antigen of the mycobacterial envelope, Phosphatidyl-myo-inositol dimannosides (PIM2) triggers Suppressor of cytokine signaling (SOCS) 3 expression in macrophages in a Toll-like receptor 2 (TLR2)-MyD88 dependent manner. Data derived from signaling perturbations suggest the involvement of phosphoinositide-3 kinase (PI3K) and protein kinase C (PKC) signaling pathways during PIM2 induced SOCS3 expression. Further, pharmacological inhibition of ERK1/2, but not of p38 MAP kinase or JNK abrogated the induced expression of SOCS3. The PIM2 induced activation of ERK1/2 was dependent on the activation of PI3K or PKC signaling which in turn regulated p65 nuclear factor -kappa B (NF-kappa B) nuclear translocation. Overall, current study delineates the role for PI3K-PKC axis and ERK1/2 signaling as key signaling events during PIM2 induced SOCS3 expression in macrophages.

A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip

The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded DSP is complex and usually custom designed with multiple banks of single-ported or dual ported on-chip scratch pad memory and multiple banks of off-chip memory. Building software for such large complex memories with many of the software components as individually optimized software IPs is a big challenge. In order to obtain good performance and a reduction in memory stalls, the data buffers of the application need to be placed carefully in different types of memory. In this paper we present a unified framework (MODLEX) that combines different data layout optimizations to address the complex DSP memory architectures. Our method models the data layout problem as multi-objective genetic algorithm (GA) with performance and power being the objectives and presents a set of solution points which is attractive from a platform design viewpoint. While most of the work in the literature assumes that performance and power are non-conflicting objectives, our work demonstrates that there is significant trade-off (up to 70%) that is possible between power and performance.

“Post silicon debug of SOC designs”

Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

The WNT Signaling Pathway Contributes to Dectin-1-Dependent Inhibition of Toll-Like Receptor-Induced Inflammatory Signature

Macrophages regulate cell fate decisions during microbial challenges by carefully titrating signaling events activated by innate receptors such as dectin-1 or Toll-like receptors (TLRs). Here, we demonstrate that dectin-1 activation robustly dampens TLR-induced proinflammatory signature in macrophages. Dectin-1 induced the stabilization of beta-catenin via spleen tyrosine kinase (Syk)-reactive oxygen species (ROS) signals, contributing to the expression of WNT5A. Subsequently, WNT5A-responsive protein inhibitors of activated STAT (PIAS-1) and suppressor of cytokine signaling 1 (SOCS-1) mediate the downregulation of IRAK-1, IRAK-4, and MyD88, resulting in decreased expression of interleukin 12 (IL-12), IL-1 beta, and tumor necrosis factor alpha (TNF-alpha). In vivo activation of dectin-1 with pathogenic fungi or ligand resulted in an increased bacterial burden of Mycobacteria, Klebsiella, Staphylococcus, or Escherichia, with a concomitant decrease in TLR-triggered proinflammatory cytokines. All together, our study establishes a new role for dectin-1-responsive inhibitory mechanisms employed by virulent fungi to limit the proinflammatory environment of the host.

A Novel and Scalable LED Communication System

We describe our novel LED communication infrastructure and demonstrate its scalability across platforms. Our system achieves 50 kilo bits per second on very simple SoCs and scales to megabits bits per second rates on dual processor based mobile phone platforms.

Ac2PIM-responsive miR-150 and miR-143 Target Receptor-interacting Protein Kinase 2 and Transforming Growth Factor Beta-activated Kinase 1 to Suppress NOD2-induced Immunomodulators

Specific and coordinated regulation of innate immune receptor-driven signaling networks often determines the net outcome of the immune responses. Here, we investigated the cross-regulation of toll-like receptor (TLR)2 and nucleotide-binding oligomerization domain (NOD)2 pathways mediated by Ac2PIM, a tetra-acylated form of mycobacterial cell wall component and muramyl dipeptide (MDP), a peptidoglycan derivative respectively. While Ac2PIM treatment of macrophages compromised their ability to induce NOD2-dependent immunomodulators like cyclooxygenase (COX)-2, suppressor of cytokine signaling (SOCS)-3, and matrix metalloproteinase (MMP)-9, no change in the NOD2-responsive NO, TNF-alpha, VEGF-A, and IL-12 levels was observed. Further, genome-wide microRNA expression profiling identified Ac2PIM-responsive miR-150 and miR-143 to target NOD2 signaling adaptors, RIP2 and TAK1, respectively. Interestingly, Ac2PIM was found to activate the SRC-FAK-PYK2-CREB cascade via TLR2 to recruit CBP/P300 at the promoters of miR-150 and miR-143 and epigenetically induce their expression. Loss-of-function studies utilizing specific miRNA inhibitors establish that Ac2PIM, via the miRNAs, abrogate NOD2-induced PI3K-PKC delta-MAPK pathway to suppress beta-catenin-mediated expression of COX-2, SOCS-3, and MMP-9. Our investigation has thus underscored the negative regulatory role of Ac2PIM-TLR2 signaling on NOD2 pathway which could broaden our understanding on vaccine potential or adjuvant utilities of Ac2PIM and/or MDP.