Reduced common-mode voltage operation of a new seven-level hybrid multilevel inverter topology with a single DC voltage source

In this study, analysis of extending the linear modulation range of a zero common-mode voltage (CMV) operated n-level inverter by allowing reduced CMV switching is presented. A new hybrid seven-level inverter topology with a single DC supply is also presented in this study and inverter operation for zero and reduced CMV is analysed. Each phase of the inverter is realised by cascading two three-level flying capacitor inverters with a half-bridge module in between. Proposed inverter topology is operated with zero CMV for modulation index <86% and is operated with a CMV magnitude of V-dc/18 to extend the modulation range up to 96%. Experimental results are presented for zero CMV operation and for reduced common voltage operation to extend the linear modulation range. A capacitor voltage balancing algorithm is designed utilising the pole voltage redundancies of the inverter, which works for every sampling instant to correct the capacitor voltage irrespective of load power factor and modulation index. The capacitor voltage balancing algorithm is tested for different modulation indices and for various transient conditions, to validate the proposed topology.

Three-level inverter fed open-end winding IM drive with common mode voltage elimination and reduced power device count

A three-level space phasor generation scheme with common mode elimination and with reduced power device count is proposed for an open end winding induction motor in this paper. The open end winding induction motor is fed by the three-level inverters from both sides. Each two level inverter is formed by cascading two two-level inverters. By sharing the bottom inverter for the two three-level inverters on either side, the power device count is reduced. The switching states with zero common mode voltage variation are selected for PWM switching so that there is no alternating common mode voltage in the pole voltages as well as in phase voltages. Only two isolated DC-links, with half the voltage rating of a conventional three-level neutral point clamped inverter, are needed for the proposed scheme.

A five level inverter scheme with common mode volatge elimination by cascading conventional two level and three level NPC inverters for an induction motor drive

Common-mode voltage generated by the PWM inverter causes shaft voltage, bearing current and ground leakage current in induction motor drive system, resulting in an early motor failure. This paper presents a common-mode elimination scheme for a five-level inverter with reduced power circuit complexity. The proposed scheme is realised by cascading conventional two-level and conventional NPC three-level inverters in conjunction with an open-end winding three-phase induction motor drive and the common-mode voltage (CMV) elimination is achieved by using only switching states that result in zero CMV, for the entire modulation range.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

Space-Vector-Based Hybrid Pulsewidth Modulation Techniques for Reduced Harmonic Distortion and Switching Loss

Novel switching sequences can be employed in spacevector-based pulsewidth modulation (PWM) of voltage source inverters. Differentswitching sequences are evaluated and compared in terms of inverter switching loss. A hybrid PWM technique named minimum switching loss PWM is proposed, which reduces the inverter switching loss compared to conventional space vector PWM (CSVPWM) and discontinuous PWM techniques at a given average switching frequency. Further, four space-vector-based hybrid PWM techniques are proposed that reduce line current distortion as well as switching loss in motor drives, compared to CSVPWM. Theoretical and experimental results are presented.

Low Power continuous time common mode sensing for common mode feedback circuits

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 mu m CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27-34% less power than previous high swing CMFB circuits.

Elimination of common mode voltage and fifth and seventh harmonics in a multilevel inverter fed IM drive using 12-sided polygonal voltage spacephasor

A multilevel inverter with 12-sided polygonal voltage space vector structure is proposed in this paper. The present scheme provides elimination of common mode voltage variation and 5(th) and 7(th) order harmonics in the entire operating range of the drive. The proposed multi level structure is achieved by cascading only the conventional two-level inverters with asymmetrical DC link voltages. The bandwidths problems associated with conventional hexagonal voltage space vector structure current controllers, due to the presence of 5(th) and 7(th) harmonics, in the over modulation region, is absent in the present 12-sided structure. So a linear voltage control up to 12-step operation is possible, from the present twelve sided scheme, with less current control complexity. An open-end winding structure is used for the induction motor drive.

A Hybrid Five-Level Inverter With Common-Mode Voltage Elimination Having Single Voltage Source for IM Drive Applications

A new hybrid five-level inverter topology with common-mode voltage (CMV) elimination for induction motor drive is proposed in this paper. This topology has only one dc source, and different voltage levels are generated by using this voltage source along with floating capacitors charged to asymmetrical voltage levels. The pulsewidth modulation (PWM) scheme employed in this topology balances the capacitor voltages at the required levels at any power factor and modulation index while eliminating the CMV. This inverter has good fault-tolerant capability as it can be operated in three-or two-level mode with CMV elimination, in case of any failure in the H-bridges. More voltage levels with CMV elimination can be realized from this topology but only in a limited range of modulation index and power factor. Extensive simulation is done to validate the PWM technique for CMV elimination and balancing of the capacitor voltages. The experimental verification of the proposed inverter-fed induction motor is carried out in the linear modulation and overmodulation regions. The steady-state and transient operations of the drive are verified. The dynamics of the capacitor voltage balancing is also tested. The experimental results demonstrate that the proposed topology can be considered for industrial drive applications.

Common-mode filter design for PWM rectifier-based motor drives

A common-mode (CM) filter based on the LCL filter topology is proposed in this paper, which provides a parallel path for ground currents and which also restricts the magnitude of the EMI noise injected into the grid. The CM filter makes use of the components of a line to line LCL filter, which is modified to address the CM voltage with minimal additional components. This leads to a compact filtering solution. The CM voltage of an adjustable speed drive using a PWM rectifier is analyzed for this purpose. The filter design is based on the CM equivalent circuit of the drive system. The filter addresses the adverse effects of the PWM rectifier in an adjustable speed drive. Guidelines are provided on the selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed circuit. Experimental results based on EMI measurement on the grid side and the CM current measurement on the motor side are presented. These results validate the effectiveness of the filter.

Common-mode voltage eliminated three-level inverter using a three-level flying-capacitor inverter and cascaded H-bridge

This paper proposes a new 3 level common mode voltage eliminated inverter using an inverter structure formed by cascading a H-Bridge with a three-level flying capacitor inverter. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-Bridge fails, the system can still be operated as a normal 3 level inverter mode at full power. This inverter has many advantages like use of single DC-supply, making it possible for a back to back grid-tied converter application, improved reliability etc.

A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

Common-Mode and Differential-Mode Active Damping for PWM Rectifiers

Modern pulse-width-modulated (PWM) rectifiers use LC L filters that can be applied in both the common mode and differential mode to obtain high-performance filtering. Interaction between the passive L and C components in the filter leads to resonance oscillations. These oscillations need to be damped either by the passive damping or active damping. The passive damping increases power loss and can reduce the effectiveness of the filter. Methods of active damping, using control strategy, are lossless while maintaining the effectiveness of the filters. In this paper, an active damping strategy is proposed to damp the oscillations in both line-to-line and line-to-ground. An approach based on pole placement by the state feedback is used to actively damp both the differential-and common-mode filter oscillations. Analytical expressions for the state-feedback controller gains are derived for both continuous and discrete-time model of the filter. Tradeoff in selection of the active damping gain on the lower order power converter harmonics is analyzed using a weighted admittance function. Experimental results on a 10-kVA laboratory prototype PWM rectifier are presented. The results validate the effectiveness of the active damping method, and the tradeoff in the settings of the damping gain.

Common-Mode Injection PWM for Parallel Converters

The ac-side terminal voltages of parallel-connected converters are different if the line reactive drops of the individual converters are different. This could result either from differences in per-phase inductances or from differences in the line currents of the converters. In such cases, the modulating signals are different for the converters. Hence, the common-mode (CM) voltages for the converters, injected by conventional space vector pulsewidth modulation (CSVPWM) to increase dc-bus utilization, are different. Consequently, significant low-frequency zero-sequence circulating currents result. This paper proposes a new modulation method for parallel-connected converters with unequal terminal voltages. This method does not cause low-frequency zero-sequence circulating currents and is comparable with CSVPWM in terms of dc-bus utilization and device power loss. Experimental results are presented at a power level of 150 kVA from a circulating-power test setup, where the differences in converter terminal voltages are quite significant.

A DC-link Capacitor Voltage Balancing with CMV Elimination using only the Switching State Redundancies for a Reduced Switch Count Multi-Level Inverter fed IM Drive

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control., using only inverter switching state redundancies. The proposed power circuit gives a simple power bits structure.

Filter Configuration and PWM Method For Single Phase Inverters with Reduced Conducted EMI Noise

Electromagnetic Interference (EMI) noise is one of the major issues during the design of the grid-tied power converters. Presence of high dv/dt in Common Mode (CM) voltage, excites the parasitic capacitances and causes injection of narrow peaky current to ground. This results in high EMI noise level. A topology consisting of a single phase PWM-rectifier with LCL filter, utilising bipolar PWM method is proposed which reduces the EMI noise level by more than 30dB. This filter topology is shown to be insensitive to the switching delays between the legs of the inverter. The proposed topology eliminates high dv/dt from the dc-bus CM voltage by making it sinusoidal. Hence, the high frequency CM current injection to ground is minimized.