A Resonant Integrator Based PLL and AC Current Controller for Single Phase Grid Connected PWM-VSI

Grid connected PWM-VSIs are being increasingly used for applications such as Distributed Generation (DG), power quality, UPS etc. Appropriate control strategies for grid synchronisation and line current regulation are required to establish such a grid interconnection and power transfer. Control of three phase VSIs is widely reported in iterature. Conventionally, dq control in Synchronous Reference Frame(SRF) is employed for both PLL and line current control where PI-controllers are used to track the DC references. Single phase systems do not have defined direct (d) and quadrature (q) axis components that are required for SRF transformation. Thus, references are AC in nature and hence usage of PI controllers cannot yield zero steady state errors. Resonant controllers have the ability to track AC references accurately. In this work, a resonant controller based single phase PLL and current control technique are being employed for tracking grid frequency and the AC current reference respectively. A single phase full bridge converter is being operated as a STATCOM for performance evaluation of the control scheme.

Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

A Novel Design Method for SOGI-PLL for Minimum Settling Time and Low Unit Vector Distortion

Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7 ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results.

A simple analog controller for single-phase half-bridge rectifier and its application to transformerless UPS

A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.

Acquisition time improvement of PLLs using some aiding functions

Analytical studies are carried out to minimize acquisition time in phase-lock loop (PLL) applications using aiding functions. A second order aided PLL is realized with the help of the quasi-stationary approach to verify the acquisition behavior in the absence of noise. Time acquisition is measured both from the study of the LPF output transient and by employing a lock detecting and indicating circuit to crosscheck experimental and analytical results. A closed form solution is obtained for the evaluation of the time acquisition using different aiding functions. The aiding signal is simple and economical and can be used with state of the art hardware.

Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.