Does lean imply green?: a study of the power performance implications of Java runtime bloat

The presence of software bloat in large flexible software systems can hurt energy efficiency. However, identifying and mitigating bloat is fairly effort intensive. To enable such efforts to be directed where there is a substantial potential for energy savings, we investigate the impact of bloat on power consumption under different situations. We conduct the first systematic experimental study of the joint power-performance implications of bloat across a range of hardware and software configurations on modern server platforms. The study employs controlled experiments to expose different effects of a common type of Java runtime bloat, excess temporary objects, in the context of the SPECPower_ssj2008 workload. We introduce the notion of equi-performance power reduction to characterize the impact, in addition to peak power comparisons. The results show a wide variation in energy savings from bloat reduction across these configurations. Energy efficiency benefits at peak performance tend to be most pronounced when bloat affects a performance bottleneck and non-bloated resources have low energy-proportionality. Equi-performance power savings are highest when bloated resources have a high degree of energy proportionality. We develop an analytical model that establishes a general relation between resource pressure caused by bloat and its energy efficiency impact under different conditions of resource bottlenecks and energy proportionality. Applying the model to different "what-if" scenarios, we predict the impact of bloat reduction and corroborate these predictions with empirical observations. Our work shows that the prevalent software-only view of bloat is inadequate for assessing its power-performance impact and instead provides a full systems approach for reasoning about its implications.

On-Chip Memory Architecture Exploration Framework for DSP Processor-Based Embedded System on Chip

Today's SoCs are complex designs with multiple embedded processors, memory subsystems, and application specific peripherals. The memory architecture of embedded SoCs strongly influences the power and performance of the entire system. Further, the memory subsystem constitutes a major part (typically up to 70%) of the silicon area for the current day SoC. In this article, we address the on-chip memory architecture exploration for DSP processors which are organized as multiple memory banks, where banks can be single/dual ported with non-uniform bank sizes. In this paper we propose two different methods for physical memory architecture exploration and identify the strengths and applicability of these methods in a systematic way. Both methods address the memory architecture exploration for a given target application by considering the application's data access characteristics and generates a set of Pareto-optimal design points that are interesting from a power, performance and VLSI area perspective. To the best of our knowledge, this is the first comprehensive work on memory space exploration at physical memory level that integrates data layout and memory exploration to address the system objectives from both hardware design and application software development perspective. Further we propose an automatic framework that explores the design space identifying 100's of Pareto-optimal design points within a few hours of running on a standard desktop configuration.

Interplay of software bloat, hardware energy proportionality and system bottlenecks

In large flexible software systems, bloat occurs in many forms, causing excess resource utilization and resource bottlenecks. This results in lost throughput and wasted joules. However, mitigating bloat is not easy; efforts are best applied where savings would be substantial. To aid this we develop an analytical model establishing the relation between bottleneck in resources, bloat, performance and power. Analyses with the model places into perspective results from the first experimental study of the power-performance implications of bloat. In the experiments we find that while bloat reduction can provide as much as 40% energy savings, the degree of impact depends on hardware and software characteristics. We confirm predictions from our model with selected results from our experimental study. Our findings show that a software-only view is inadequate when assessing the effects of bloat. The impact of bloat on physical resource usage and power should be understood for a full systems perspective to properly deploy bloat reduction solutions and reap their power-performance benefits.

Three-Dimensional Nanoarchitecture of BiFeO3 Anchored TiO2 Nanotube Arrays for Electrochemical Energy Storage and Solar Energy Conversion

Here, we report the synthesis of TiO2/BiFeO3 nano-heterostnicture (NH) arrays by anchoring BiFeO3 (BFO) particles on on TiO2 nanotube surface and investigate their pseudocapacitive and photoelectrochemical properties considering their applications in green energy fields. The unique TiO2/BFO NHs have been demonstrated both as energy conversion and storage materials. The capacitive behavior of the NHs has been found to be significantly higher than that of the pristine TiO2 NTs, which is mainly due to the anchoring of redox active BFO nanoparticles. A specific capacitance of about 440 F g(-1) has been achieved for this NHs at a current density of 1.1 A g(-1) with similar to 80% capacity retention at a current density of 2.5 A g(-1). The NHs also exhibit high energy and power performance (energy density of 46.5 Wh kg(-1) and power density of 1.2 kW kg(-1) at a current density of 2.5 A g(-1)) with moderate cycling stability (92% capacity retention after 1200 cycles). Photoelectrochemical investigation reveals that the photocurrent density of the NHs is almost 480% higher than the corresponding dark current and it shows significantly improved photoswitching performance as compared to pure TiO2 nanotubes, which has been demonstrated based the interfacial type-II band alignment between TiO2 and BFO.

Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Optimal simultaneous maximum a posterioriestimation of states, noise statistics and parameters II. Numerical performance

A very general and numerically quite robust algorithm has been proposed by Sastry and Gauvrit (1980) for system identification. The present paper takes it up and examines its performance on a real test example. The example considered is the lateral dynamics of an aircraft. This is used as a vehicle for demonstrating the performance of various aspects of the algorithm in several possible modes.

Analysis of the performance characteristics of a two-inertia power transmission system with a plate clutch

The performance of a plate clutch in a two-inertia power transmission system is analysed assuming negligible compliance and using a piecewise linear function to represent the clutch torque characteristic. Expressions defining, for all linear segments of the clutch torque characteristic, dimensionless input and output velocities of the clutch and dimensionless slip period are presented. The use of these expressions in preparing design charts to aid analysis and design of the plate clutch is outlined.

Joint Power Control, Scheduling and Routing for Multihop Energy Harvesting Sensor Networks

We study wireless multihop energy harvesting sensor networks employed for random field estimation. The sensors sense the random field and generate data that is to be sent to a fusion node for estimation. Each sensor has an energy harvesting source and can operate in two modes: Wake and Sleep. We consider the problem of obtaining jointly optimal power control, routing and scheduling policies that ensure a fair utilization of network resources. This problem has a high computational complexity. Therefore, we develop a computationally efficient suboptimal approach to obtain good solutions to this problem. We study the optimal solution and performance of the suboptimal approach through some numerical examples.

Performance study of high operating temperature HgCdTe mid wave infrared detector through numerical modeling

The design of present generation uncooled Hg1-xCdxTe infrared photon detectors relies on complex heterostructures with a basic unit cell of type (n) under bar (+)/pi/(p) under bar (+). We present an analysis of double barrier (n) under bar (+)/pi/(p) under bar (+) mid wave infrared (x = 0.3) HgCdTe detector for near room temperature operation using numerical computations. The present work proposes an accurate and generalized methodology in terms of the device design, material properties, and operation temperature to study the effects of position dependence of carrier concentration, electrostatic potential, and generation-recombination (g-r) rates on detector performance. Position dependent profiles of electrostatic potential, carrier concentration, and g-r rates were simulated numerically. Performance of detector was studied as function of doping concentration of absorber and contact layers, width of both layers and minority carrier lifetime. Responsivity similar to 0.38 A W-1, noise current similar to 6 x 10(-14) A/Hz(1/2) and D* similar to 3.1 x 10(10)cm Hz(1/2) W-1 at 0.1 V reverse bias have been calculated using optimized values of doping concentration, absorber width and carrier lifetime. The suitability of the method has been illustrated by demonstrating the feasibility of achieving the optimum device performance by carefully selecting the device design and other parameters. (C) 2010 American Institute of Physics. doi:10.1063/1.3463379]

Performance comparison of batch and continuous flow surface aeration systems

The oxygen transfer rate and the corresponding power requirement to operate the rotor are vital for design and scale-up of surface aerators. The aeration process can be analyzed in two ways such as batch and continuous systems. The process behaviors of batch and continuous flow systems are different from each other. The experimental and numerical results obtained through the batch systems cannot be relied on and applied for the designing of the continuous aeration tank. Based on the experimentation on batch and continuous type systems, the present work compares the performance of both the batch and continuous surface aeration systems in terms of their oxygen transfer capacity and power consumption. A simulation equation developed through experimentation has shown that continuous flow surface aeration systems are taking more energy than the batch systems. It has been found that batch systems are economical and better for the field application but not feasible where large quantity of wastewater is produced.

Effect of uncertainty on helicopter performance predictions

The effect of uncertainties on performance predictions of a helicopter is studied in this article. The aeroelastic parameters such as the air density, blade profile drag coefficient, main rotor angular velocity, main rotor radius, and blade chord are considered as uncertain variables. The propagation of these uncertainties in the performance parameters such as thrust coefficient, figure of merit, induced velocity, and power required are studied using Monte Carlo simulation and the first-order reliability method. The Rankine-Froude momentum theory is used for performance prediction in hover, axial climb, and forward flight. The propagation of uncertainty causes large deviations from the baseline deterministic predictions, which undoubtedly affect both the achievable performance and the safety of the helicopter. The numerical results in this article provide useful bounds on helicopter power requirements.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Numerical Study Of Heat Transfer From Pin Fin Heat Sink Using Steady And Pulsated Impinging Jets

The work reported in this thesis is an attempt to enhance heat transfer in electronic devices with the use of impinging air jets on pin-finned heat sinks. The cooling per-formance of electronic devices has attracted increased attention owing to the demand of compact size, higher power densities and demands on system performance and re-liability. Although the technology of cooling has greatly advanced, the main cause of malfunction of the electronic devices remains overheating. The problem arises due to restriction of space and also due to high heat dissipation rates, which have increased from a fraction of a W/cm2to 100s of W /cm2. Although several researchers have at-tempted to address this at the design stage, unfortunately the speed of invention of cooling mechanism has not kept pace with the ever-increasing requirement of heat re- moval from electronic chips. As a result, efficient cooling of electronic chip remains a challenge in thermal engineering. Heat transfer can be enhanced by several ways like air cooling, liquid cooling, phase change cooling etc. However, in certain applications due to limitations on cost and weight, eg. air borne application, air cooling is imperative. The heat transfer can be increased by two ways. First, increasing the heat transfer coefficient (forced convec- tion), and second, increasing the surface area of heat transfer (finned heat sinks). From previous literature it was established that for a given volumetric air flow rate, jet im-pingement is the best option for enhancing heat transfer coefficient and for a given volume of heat sink material pin-finned heat sinks are the best option because of their high surface area to volume ratio. There are certain applications where very high jet velocities cannot be used because of limitations of noise and presence of delicate components. This process can further be improved by pulsating the jet. A steady jet often stabilizes the boundary layer on the surface to be cooled. Enhancement in the convective heat transfer can be achieved if the boundary layer is broken. Disruptions in the boundary layer can be caused by pulsating the impinging jet, i.e., making the jet unsteady. Besides, the pulsations lead to chaotic mixing, i.e., the fluid particles no more follow well defined streamlines but move unpredictably through the stagnation region. Thus the flow mimics turbulence at low Reynolds number. The pulsation should be done in such a way that the boundary layer can be disturbed periodically and yet adequate coolant is made available. So, that there is not much variation in temperature during one pulse cycle. From previous literature it was found that square waveform is most effective in enhancing heat transfer. In the present study the combined effect of pin-finned heat sink and impinging slot jet, both steady and unsteady, has been investigated for both laminar and turbulent flows. The effect of fin height and height of impingement has been studied. The jets have been pulsated in square waveform to study the effect of frequency and duty cycle. This thesis attempts to increase our understanding of the slot jet impingement on pin-finned heat sinks through numerical investigations. A systematic study is carried out using the finite-volume code FLUENT (Version 6.2) to solve the thermal and flow fields. The standard k-ε model for turbulence equations and two layer zonal model in wall function are used in the problem Pressure-velocity coupling is handled using the SIMPLE algorithm with a staggered grid. The parameters that affect the heat transfer coefficient are: height of the fins, total height of impingement, jet exit Reynolds number, frequency of the jet and duty cycle (percentage time the jet is flowing during one complete cycle of the pulse). From the studies carried out it was found that: a) beyond a certain height of the fin the rate of enhancement of heat transfer becomes very low with further increase in height, b) the heat transfer enhancement is much more sensitive to any changes at low Reynolds number than compared to high Reynolds number, c) for a given total height of impingement the use of fins and pulsated jet, increases the effective heat transfer coefficient by almost 200% for the same average Reynolds number, d) for all the cases it was observed that the optimum frequency of impingement is around 50 − 100 Hz and optimum duty cycle around 25-33.33%, e) in the case of turbulent jets the enhancement in heat transfer due to pulsations is very less compared to the enhancement in case of laminar jets.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.