Ellipsometry as a Sensitive Technique to Probe film -Substrate Interfaces: Al2O3 on Si(100)

An attempt has been made to study the film-substrate interface by using a sensitive, non- conventional tool. Because of the prospective use of gate oxide in MOSFET devices, we have chosen to study alumina films grown on silicon. Film-substrate interface of alumina grown by MOCVD on Si(100) was studied systematically using spectroscopic ellipsometry in the range 1.5-5.0 eV, supported by cross-sectional SEM, and SIMS. The (ε1,ε2) versus energy data obtained for films grown at 600°C, 700°C, and 750°C were modeled to fit a substrate/interface/film “sandwich”. The experimental results reveal (as may be expected) that the nature of the substrate -film interface depends strongly on the growth temperature. The simulated (ε1,ε2) patterns are in excellent agreement with observed ellipsometric data. The MOCVD precursors results the presence of carbon in the films. Theoretical simulation was able to account for the ellipsometry data by invoking the presence of “free” carbon in the alumina films.

Part II: Design of Well Doping Profile for Improved Breakdown and Mixed-Signal Performance of STI-Type DePMOS Device

Shallow-trench isolation drain extended pMOS (STI-DePMOS) devices show a distinct two-stage breakdown. The impact of p-well and deep-n-well doping profile on breakdown characteristics is investigated based on TCAD simulations. Design guidelines for p-well and deep-n-well doping profile are developed to shift the onset of the first-stage breakdown to a higher drain voltage and to avoid vertical punch-through leading to early breakdown. An optimal ratio between the OFF-state breakdown voltage and the ON-state resistance could be obtained. Furthermore, the impact of p-well/deep-n-well doping profile on the figure of merits of analog and digital performance is studied. This paper aids in the design of STI drain extended MOSFET devices for widest safe operating area and optimal mixed-signal performance in advanced system-on-chip input-output process technologies.

Analytical modeling of quantum threshold voltage for triple gate MOSFET

In this work a physically based analytical quantum threshold voltage model for the triple gate long channel metal oxide semiconductor field effect transistor is developed The proposed model is based on the analytical solution of two-dimensional Poisson and two-dimensional Schrodinger equation Proposed model is extended for short channel devices by including semi-empirical correction The impact of effective mass variation with film thicknesses is also discussed using the proposed model All models are fully validated against the professional numerical device simulator for a wide range of device geometries (C) 2010 Elsevier Ltd All rights reserved

Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.

Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET

A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.

Piecewise Linearization Technique for Compact Charge Modeling of Independent DG MOSFET

Charge linearization techniques have been used over the years in advanced compact models for bulk and double-gate MOSFETs in order to approximate the position along the channel as a quadratic function of the surface potential (or inversion charge densities) so that the terminal charges can be expressed as a compact closed-form function of source and drain end surface potentials (or inversion charge densities). In this paper, in case of the independent double-gate MOSFETs, we show that the same technique could be used to model the terminal charges quite accurately only when the 1-D Poisson solution along the channel is fully hyperbolic in nature or the effective gate voltages are same. However, for other bias conditions, it leads to significant error in terminal charge computation. We further demonstrate that the amount of nonlinearity that prevails between the surface potentials along the channel actually dictates if the conventional charge linearization technique could be applied for a particular bias condition or not. Taking into account this nonlinearity, we propose a compact charge model, which is based on a novel piecewise linearization technique and shows excellent agreement with numerical and Technology Computer-Aided Design (TCAD) simulations for all bias conditions and also preserves the source/drain symmetry which is essential for Radio Frequency (RF) circuit design. The model is implemented in a professional circuit simulator through Verilog-A, and simulation examples for different circuits verify good model convergence.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Bipolar Poisson Solution for Independent Double-Gate MOSFET

We propose a new set of input voltage equations (IVEs) for independent double-gate MOSFET by solving the governing bipolar Poisson equation (PE) rigorously. The proposed IVEs, which involve the Legendre's incomplete elliptic integral of the first kind and Jacobian elliptic functions and are valid from accumulation to inversion regimes, are shown to have good agreement with the numerical solution of the same PE for all bias conditions.

Performance Analysis of Strained Monolayer MoS2 MOSFET

We present a computational study on the impact of tensile/compressive uniaxial (epsilon(xx)) and biaxial (epsilon(xx) = epsilon(yy)) strain on monolayer MoS2, n-, and p-MOSFETs. The material properties like band structure, carrier effective mass, and the multiband Hamiltonian of the channel are evaluated using the density functional theory. Using these parameters, self-consistent Poisson-Schrodinger solution under the nonequilibrium Green's function formalism is carried out to simulate the MOS device characteristics. 1.75% uniaxial tensile strain is found to provide a minor (6%) ON current improvement for the n-MOSFET, whereas same amount of biaxial tensile strain is found to considerably improve the p-MOSFET ON currents by 2-3 times. Compressive strain, however, degrades both n-MOS and p-MOS devices performance. It is also observed that the improvement in p-MOSFET can be attained only when the channel material becomes indirect gap in nature. We further study the performance degradation in the quasi-ballistic long-channel regime using a projected current method.

A Short-Channel Common Double-Gate MOSFET Model Adapted to Gate Oxide Thickness Asymmetry

Existing compact models for common double-gate (CDG) MOSFETs are based on the fundamental assumption of having symmetric gate oxide thickness. In this paper, we demonstrate that using the unique quasi-linear relationship between the surface potentials, it is possible to develop compact model for CDG-MOSFETs without such approximation while preserving the mathematical complexity at the same level of the existing models. In the proposed model, the surface potential relationship is used to include the drain-induced barrier lowering, channel length modulation, velocity saturation, and quantum mechanical effect in the long-channel model and good agreement is observed with the technology computer aided design simulation results.

Phonon scattering limited performance of monolayer MoS2 and WSe2 n-MOSFET

In this paper we show the effect of electron-phonon scattering on the performance of monolayer (1L) MoS2 and WSe2 channel based n-MOSFETs. Electronic properties of the channel materials are evaluated using the local density approximation (LDA) in density functional theory (DFT). For phonon dispersion we employ the small displacement / frozen phonon calculations in DFT. Thereafter using the non-equilibrium Green's function (NEGF) formalism, we study the effect of electron-phonon scattering and the contribution of various phonon modes on the performance of such devices. It is found that the performance of the WSe2 device is less impacted by phonon scattering, showing a ballisticity of 83% for 1L-WSe2 FET for channel length of 10 nm. Though 1L-MoS2 FET of similar dimension shows a lesser ballisticity of 75%. Also in the presence of scattering there exist a a 21-36% increase in the intrinsic delay time (tau) and a 10-18% reduction in peak transconductance (g(m)) for WSe2 and MoS2 devices respectively. (C) 2015 Author(s).

Sizable photocurrent and emission from solid state devices based on CdS nanoparticles

CdS nanoparticles exhibit size dependent optical and electrical properties. We report here the photocurrent and I-V characteristic studies of CdS nanoparticle devices. A sizable short circuit photocurrent was observed in the detection range governed by the size of the clusters. We speculate on the mechanisms leading to the photocurrent and emission in these nanometer scale systems.

Use of narrow-pore filters in He II transfer devices - new results

With the aim of finding simple methods for the fabrication of He II refilling devices, He II flow has been studied through filters made from various fine powders (oxides and metals, grain sizes in the range 0.05–2 μm) by compacting them under pressure. The results obtained for the different states of He II flow, especially in the “breakthrough” and “easy flow” range, are explained by the fountain effect, He II hydrodynamics and the choking effect. According to the results, pressedpowder filters can be classified into three groups with different flow characteristics, of which the “good transfer filters” with a behaviour neatly described by simple theory are suitable for use in He II refilling devices.

Resistance Noise in Graphene Based Field Effect Devices

We present a low-frequency electrical noise measurement in graphene based field effect transistors. For single layer graphene (SLG), the resistance fluctuations is governed by the screening of the charge impurities by the mobile charges. However, in case of Bilayer graphene (BLG), the electrical noise is strongly connected to its band structure, and unlike single layer graphene, displays a minimum when the gap between the conduction and valence band is zero. Using double gated BLG devices we have tuned the zero gap and charge neutrality points independently, which offers a versatile mechanism to investigate the low-energy band structure, charge localization and screening properties of bilayer graphene