136 resultados para JUNCTIONLESS NANOWIRE TRANSISTORS (JNTS)
em Indian Institute of Science - Bangalore - Índia
Resumo:
In this work, for the first time, we present a physically based analytical threshold voltage model for omega gate silicon nanowire transistor. This model is developed for long channel cylindrical body structure. The potential distribution at each and every point of the of the wire is derived with a closed form solution of two dimensional Poisson's equation, which is then used to model the threshold voltage. Proposed model can be treated as a generalized model, which is valid for both surround gate and semi-surround gate cylindrical transistors. The accuracy of proposed model is verified for different device geometry against the results obtained from three dimensional numerical device simulators and close agreement is observed.
Resumo:
We report on multifunctional devices based on CNT arrays-ZnO nanowires hybrid architectures. The hybrid structure exhibit excellent high current Schottky like behavior with ZnO as p-type and an ideality factor close to the ideal value. Further the CNT-ZnO hybrid structures can be used as high current p-type field effect transistors that can deliver currents of the order of milliamperes and also can be used as ultraviolet detectors with controllable current on-off ratio and response time. The p-type nature of ZnO and possible mechanism for the rectifying characteristics of CNT-ZnO has been presented.
Resumo:
As the conventional MOSFET's scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible candidate in terms of technology in sub-45nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body is used to sustain the channel. There exits a disparity in threshold voltage calculation criteria of undoped-body symmetric double gate transistors which uses two definitions, one is potential based and the another is charge based definition. In this paper, a novel concept of "crossover point'' is introduced, which proves that the charge-based definition is more accurate than the potential based definition.The change in threshold voltage with body thickness variation for a fixed channel length is anomalous as predicted by potential based definition while it is monotonous for charge based definition.The threshold voltage is then extracted from drain currant versus gate voltage characteristics using linear extrapolation and "Third Derivative of Drain-Source Current'' method or simply "TD'' method. The trend of threshold voltage variation is found same in both the cases which support charge-based definition.
Resumo:
As the conventional MOSFETs scaling is approaching the limit imposed by short channel effects, Double Gate (DG) MOS transistors are appearing as the most feasible andidate in terms of technology in sub-45nm technology nodes. As the short channel effect in DG transistor is controlled by the device geometry, undoped or lightly doped body, is used to sustain the channel. There exits a disparity in threshold voltage calculation criteria of undoped-body symmetric double gate transistors which uses two definitions, one is potential based and the another is charge based definition. In this paper, a novel concept of "crossover point" is introduced, which proves that the charge-based definition is more accurate than the potential based definition. The change in threshold voltage with body thickness variation for a fixed channel length is anomalous as predicted by, potential based definition while it is monotonous for change based definition. The threshold voltage is then extracted from drain currant versus gate voltage characteristics using linear extrapolation and "Third Derivative of Drain-Source Current" method or simply "TD" method. The trend of threshold voltage variation is found some in both the cases which support charge-based definition.
Resumo:
This paper describes a new analysis of the avalanche breakdown phenomenon in bipolar transistors for different bias conditions of the emitter-base junction. This analysis revolves around the transportation and storage of majority carriers in the base region. Using this analysis one can compute all the voltage-current characteristics of a transistor under avalanche breakdown.
Resumo:
Two different definitions, one is potential based and the other is charge based, are used in the literatures to define the threshold voltage of undoped body symmetric double gate transistors. This paper, by introducing a novel concept of crossover point, proves that the charge based definition is more accurate than the potential based definition. It is shown that for a given channel length the potential based definition predicts anomalous change in threshold voltage with body thickness variation while the charge based definition results in monotonous change. The threshold voltage is then extracted from drain current versus gate voltage characteristics using linear extrapolation, transconductance and match-point methods. In all the three cases it is found that trend of threshold voltage variation support the charge based definition.
Resumo:
In the present paper, the size and strain rate effects on ultra-thin < 100 >/{100} Cu nanowires at an initial temperature of 10 K have been discussed. Extensive molecular dynamics (MD) simulations have been performed using Embedded atom method (EAM) to investigate the structural behaviours and properties under high strain rate. Velocity-Verlet algorithm has been used to solve the equation of motions. Two different thermal loading cases have been considered: (i) Isothermal loading, in which Nose-Hoover thermostat is used to maintain the constant system temperature, and (ii) Adiabatic loading, i.e., without any thermostat. Five different wire cross-sections were considered ranging from 0.723 x 0.723 nm(2) to 2.169 x 2.169 nm(2) The strain rates used in the present study were 1 x 10(9) s(-1), 1 x 10(8) s(-1), and 1 x 10(7) s(-1). The effect of strain rate on the mechanical properties of copper nanowires was analysed, which shows that elastic properties are independent of thermal loading for a given strain rate and cross-sectional dimension of nanowire. It showed a decreasing yield stress and yield strain with decreasing strain rate for a given cross- section. Also, a decreasing yield stress and increasing yield strain were observed for a given strain rate with increasing cross-sectional area. Elastic modulus was found to be similar to 100 GPa, which was independent of processing temperature, strain rate, and size for a given initial temperature. Reorientation of < 100 >/{100} square cross-sectional copper nanowire into a series of stable ultra-thin Pentagon copper nanobridge structures with dia of similar to 1 nm at 10 K was observed under high strain rate tensile loading. The effect of isothermal and adiabatic loading on the formation of such pentagonal nanobridge structure has been discussed.
Resumo:
A simplified yet analytical approach on few ballistic properties of III-V quantum wire transistor has been presented by considering the band non-parabolicity of the electrons in accordance with Kane's energy band model using the Bohr-Sommerfeld's technique. The confinement of the electrons in the vertical and lateral directions are modeled by an infinite triangular and square well potentials respectively, giving rise to a two dimensional electron confinement. It has been shown that the quantum gate capacitance, the drain currents and the channel conductance in such systems are oscillatory functions of the applied gate and drain voltages at the strong inversion regime. The formation of subbands due to the electrical and structural quantization leads to the discreetness in the characteristics of such 1D ballistic transistors. A comparison has also been sought out between the self-consistent solution of the Poisson's-Schrodinger's equations using numerical techniques and analytical results using Bohr-Sommerfeld's method. The results as derived in this paper for all the energy band models gets simplified to the well known results under certain limiting conditions which forms the mathematical compatibility of our generalized theoretical formalism.
Resumo:
A novel stress induced martenistic phase transformation is reported in an initial B2-CuZr nanowire of cross-sectional dimensions in the range of 19.44 x 19.44-38.88 x 38.88 angstrom(2) and temperature in the range of 10-400 K under both tensile and compressive loading. Extensive Molecular Dynamic simulations are performed using an inter-atomic potential of type Finnis and Sinclair. The nanowire shows a phase transformation from an initial B2 phase to BCT (body-centered-tetragonal) phase with failure strain of similar to 40% in tension, whereas in compression, comparatively a small B2 -> BCT phase transformation is observed with failure strain of similar to 25%. Size and temperature dependent deformation mechanisms which control ultimately the B2 -> BCT phase transformation are found to be completely different for tensile and compressive loadings. Under tensile loading, small cross-sectional nanowire shows a single step phase transformation, i.e. B2 -> BCT via twinning along {100} plane, whereas nanowires with larger cross-sectional area show a two step phase transformation, i.e. B2 -> R phase -> BCT along with intermediate hardening. In the first step, nanowire shows phase transformation from B2 -> R phase via twinning along {100} plane, afterwards the nanowire deforms via twinning along {110} plane which cause further transformation from R phase -> BCT phase. Under compressive loading, the nanowire shows crushing along {100} plane after a single step phase transformation from B2 -> BCT. Proper tailoring of such size and temperature dependent phase transformation can be useful in designing nanowire for high strength applications with corrosion and fatigue resistance. (C) 2009 Elsevier Ltd. All rights reserved.
Resumo:
Field-effect transistor characteristics of few-layer graphenes prepared by several methods have been investigated in comparison with those of single-layer graphene prepared by the in situ reduction of single-layer graphene oxide. Ambipolar features have been observed with single-layer graphene and n-type behaviour with all the few-layer graphenes, the best characteristics being found with the graphene possessing 2-3 layers prepared by arc-discharge of graphite in hydrogen. FETs based on boron and nitrogen doped graphene show n-type and p-type behaviour respectively. (C) 2010 Elsevier Ltd. All rights reserved.
Resumo:
Previous techniques used for solving the 1-D Poisson equation ( PE) rigorously for long-channel asymmetric and independent double-gate (IDG) transistors result in potential models that involve multiple intercoupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This paper reports a different rigorous technique for solving the same PE by which one can obtain the potential profile of a generalized IDG transistor that involves a single implicit equation. The proposed Poisson solution is shown to be computationally more efficient for circuit simulation than the previous solutions.
Resumo:
The asymmetric stress strain behavior under tension/compression in an initial < 100 > B-2-NiAl nanowire is investigated considering two different surface configurations i.e., < 100 >/(0 1 0) (0 0 1) and < 100 >/(0 1 1) (0 - 1 1). This behavior is attributed to two different deformation mechanisms namely a slip dominated deformation under compression and a known twinning dominated deformation under tension. It is also shown that B2 -> BCT (body-centered-tetragonal) phase transformation under tensile loading is independent of the surface configurations for an initial < 100 > oriented NiAl nanowire. Under tensile loading, the nanowire undergoes a stress-induced martensiticphase transformation from an initial B2 phase to BCT phase via twinning along {110} plane with failure strain of similar to 0.30. On the other hand, a compressive loading causes failure of these nanowires via brittle fracture after compressive yielding, with a maximum failure strain of similar to-0.12. Such brittle fracture under compressive loading occurs via slip along {110} plane without any phase transformations. Softening/hardening behavior is also reported for the first time in these nanowires under tensile/compressive loadings, which cause asymmetry in their yield strength behavior in the stress strain space. Result shows that a sharp increase in energy with increasing strain under compressive loading causes hardening of the nanowire, and hence, gives improved yield strength as compared to tensile loading. (C) 2010 Elsevier Ltd. All rights reserved.
Resumo:
This paper presents an analysis of the effects of ambients-temperature and light intensity on the V-l characteristics of bipolar transistors under electrical breakdown. The analysis is based on the transportation and storage of majority carriers in the base region. It is shown that this analysis can explain the observed shift in the V-l characteristics to lower voltages with increase in either temperature or light intensity.
Resumo:
In this paper, we focus on the performance of a nanowire field-effect transistor in the ultimate quantum capacitance limit (UQCL) (where only one subband is occupied) in the presence of interface traps (D-it), parasitic capacitance (C-L), and source/drain series resistance (R-s,R-d), using a ballistic transport model and compare the performance with its classical capacitance limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely: 1) gate capacitance; 2) drain-current saturation; 3) subthreshold slope; and 4) scaling performance. To gain physical insights into these effects, we also develop a set of semianalytical equations. The key observations are as follows: 1) A strongly energy-quantized nanowire shows nonmonotonic multiple-peak C-V characteristics due to discrete contributions from individual subbands; 2) the ballistic drain current saturates better in the UQCL than in the CCL, both in the presence and absence of D-it and R-s,R-d; 3) the subthreshold slope does not suffer any relative degradation in the UQCL compared to the CCL, even with Dit and R-s,R-d; 4) the UQCL scaling outperforms the CCL in the ideal condition; and 5) the UQCL scaling is more immune to R-s,R-d, but the presence of D-it and C-L significantly degrades the scaling advantages in the UQCL.
Resumo:
The small signal ac response is measured across the source-drain terminals of organic field-effect transistors (OFET) under dc bias to obtain the equivalent circuit parameters of poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT) and poly(3-hexyl thiophene) (P3HT) based devices. The numerically simulated response based on these parameters is in good agreement with the experimental data for PBTTT-FET except at low frequencies, while the P3HT-FET data show significant deviations. This indicates that the interface with the metal electrode is rather complex for the latter, involving additional circuit elements arising from contact impedance or charge injection processes. Such an investigation can help in identifying the operational bottlenecks and to improve the performance of OFETs.