Heterologous promoter recognition leading to high-level expression of cloned foreign genes in Bombyx mori cell lines and larvae

The baculovirus expression system using the Autographa californica nuclear polyhedrosis virus (AcNPV) has been extensively utilized for high-level expression of cloned foreign genes, driven by the strong viral promoters of polyhedrin (polh) and p10 encoding genes. A parallel system using Bombyx mori nuclear polyhedrosis virus (BmNPV) is much less exploited because the choice and variety of BmNPV-based transfer vectors are limited. Using a transient expression assay, we have demonstrated here that the heterologous promoters of the very late genes polh and p10 from AcNPV function as efficiently in BmN cells as the BmNPV promoters. The location of the cloned foreign gene with respect to the promoter sequences was critical for achieving the highest levels of expression, following the order +35 > +1 > -3 > -8 nucleotides (nt) with respect to the polh or p10 start codons. We have successfully generated recombinant BmNPV harboring AcNPV promoters by homeologous recombination between AcNPV-based transfer vectors and BmNPV genomic DNA. Infection of BmN cell lines with recombinant BmNPV showed a temporal expression pattern, reaching very high levels in 60-72 h post infection. The recombinant BmNPV harboring the firefly luciferase-encoding gene under the control of AcNPV polh or p10 promoters, on infection of the silkworm larvae led to the synthesis of large quantities of luciferase. Such larvae emanated significant luminiscence instantaneously on administration of the substrate luciferin resulting in 'glowing silkworms'. The virus-infected larvae continued to glow for several hours and revealed the most abundant distribution of virus in the fat bodies. In larval expression also, the highest levels were achieved when the reporter gene was located at +35 nt of the polh.

Implications of high level pseudogene transcription in Mycobacterium leprae

Background: The Mycobacterium leprae genome has less than 50% coding capacity and 1,133 pseudogenes. Preliminary evidence suggests that some pseudogenes are expressed. Therefore, defining pseudogene transcriptional and translational potentials of this genome should increase our understanding of their impact on M. leprae physiology. Results: Gene expression analysis identified transcripts from 49% of all M. leprae genes including 57% of all ORFs and 43% of all pseudogenes in the genome. Transcribed pseudogenes were randomly distributed throughout the chromosome. Factors resulting in pseudogene transcription included: 1) co-orientation of transcribed pseudogenes with transcribed ORFs within or exclusive of operon-like structures; 2) the paucity of intrinsic stem-loop transcriptional terminators between transcribed ORFs and downstream pseudogenes; and 3) predicted pseudogene promoters. Mechanisms for translational ``silencing'' of pseudogene transcripts included the lack of both translational start codons and strong Shine-Dalgarno (SD) sequences. Transcribed pseudogenes also contained multiple ``in-frame'' stop codons and high Ka/Ks ratios, compared to that of homologs in M. tuberculosis and ORFs in M. leprae. A pseudogene transcript containing an active promoter, strong SD site, a start codon, but containing two in frame stop codons yielded a protein product when expressed in E. coli. Conclusion: Approximately half of M. leprae's transcriptome consists of inactive gene products consuming energy and resources without potential benefit to M. leprae. Presently it is unclear what additional detrimental affect(s) this large number of inactive mRNAs has on the functional capability of this organism. Translation of these pseudogenes may play an important role in overall energy consumption and resultant pathophysiological characteristics of M. leprae. However, this study also demonstrated that multiple translational ``silencing'' mechanisms are present, reducing additional energy and resource expenditure required for protein production from the vast majority of these transcripts.

High-level expression of biologically active glycoprotein hormones in Pichia pastoris strains—selection of strain GS115, and not X-33, for the production of biologically active N-glycosylated 15N-labeled phCG

The methylotrophic yeast Pichia pastoris is widely used for the production of recombinant glycoproteins. With the aim to generate biologically active 15N-labeled glycohormones for conformational studies focused on the unravelling of the NMR structures in solution, the P. pastoris strains GS115 and X-33 were explored for the expression of human chorionic gonadotropin (phCG) and human follicle-stimulating hormone (phFSH). In agreement with recent investigations on the N-glycosylation of phCG, produced in P. pastoris GS115, using ammonia/glycerol-methanol as nitrogen/carbon sources, the N-glycosylation pattern of phCG, synthesized using NH4Cl/glucose–glycerol–methanol, comprised neutral and charged, phosphorylated high-mannose-type N-glycans (Man8–15GlcNAc2). However, the changed culturing protocol led to much higher amounts of glycoprotein material, which is of importance for an economical realistic approach of the aimed NMR research. In the context of these studies, attention was also paid to the site specific N-glycosylation in phCG produced in P. pastoris GS115. In contrast to the rather simple N-glycosylation pattern of phCG expressed in the GS115 strain, phCG and phFSH expressed in the X-33 strain revealed, besides neutral high-mannose-type N-glycans, also high concentrations of neutral hypermannose-type N-glycans (Manup-to-30GlcNAc2). The latter finding made the X-33 strain not very suitable for generating 15N-labeled material. Therefore, 15N-phCG was expressed in the GS115 strain using the new optimized protocol. The 15N-enrichment was evaluated by 15N-HSQC NMR spectroscopy and GLC-EI/MS. Circular dichroism studies indicated that 15N-phCG/GS115 had the same folding as urinary hCG. Furthermore, 15N-phCG/GS115 was found to be similar to the unlabeled protein in every respect as judged by radioimmunoassay, radioreceptor assays, and in vitro bioassays.

Ordered Ports – a Language Concept for High-level Distributed Programming

A new language concept for high-level distributed programming is proposed. Programs are organised as a collection of concurrently executing processes. Some of these processes, referred to as liaison processes, have a monitor-like structure and contain ports which may be invoked by other processes for the purposes of synchronisation and communication. Synchronisation is achieved by conditional activation of ports and also through port control constructs which may directly specify the execution ordering of ports. These constructs implement a path-expression-like mechanism for synchronisation and are also equipped with options to provide conditional, non-deterministic and priority ordering of ports. The usefulness and expressive power of the proposed concepts are illustrated through solutions of several representative programming problems. Some implementation issues are also considered.

Translational Up-Regulation and High-Level Protein Expression from Plasmid Vectors by mTOR Activation via Different Pathways in PC3 and 293T Cells

Background: Though 293T cells are widely used for expression of proteins from transfected plasmid vectors, the molecular basis for the high-level expression is yet to be understood. We recently identified the prostate carcinoma cell line PC3 to be as efficient as 293T in protein expression. This study was undertaken to decipher the molecular basis of high-level expression in these two cell lines. Methodology/Principal Findings: In a survey of different cell lines for efficient expression of platelet-derived growth factor-B (PDGF-B), beta-galactosidase (beta-gal) and green fluorescent protein (GFP) from plasmid vectors, PC3 was found to express at 5-50-fold higher levels compared to the bone metastatic prostate carcinoma cell line PC3BM and many other cell lines. Further, the efficiency of transfection and level of expression of the reporters in PC3 were comparable to that in 293T. Comparative analyses revealed that the high level expression of the reporters in the two cell lines was due to increased translational efficiency. While phosphatidic acid (PA)-mediated activation of mTOR, as revealed by drastic reduction in reporter expression by n-butanol, primarily contributed to the high level expression in PC3, multiple pathways involving PA, PI3K/Akt and ERK1/2 appear to contribute to the abundant reporter expression in 293T. Thus the extent of translational upregulation attained through the concerted activation of mTOR by multiple pathways in 293T could be achieved through its activation primarily by the PA pathway in PC3. Conclusions/Significance: Our studies reveal that the high-level expression of proteins from plasmid vectors is effected by translational up-regulation through mTOR activation via different signaling pathways in the two cell lines and that PC3 is as efficient as 293T for recombinant protein expression. Further, PC3 offers an advantage in that the level of expression of the protein can be regulated by simple addition of n-butanol to the culture medium.

High level stable expression of rat brain type IIA sodium channel ?-subunit in CHO cells

The neuronal sodium channels are responsible for the rising phase of action potential and are composed of three subunits, of which the alpha-subunit has been shown to be adequate for most of its functional properties. We have stably expressed the rat brain type IIA sodium channel alpha-subunit in CHO cell tine using a CMV promoter-based vector. The expression was confirmed by detecting a 6.5 kb RNA corresponding to sodium channel alpha-subunit using Northern hybridization. The cells stably expressing the alpha-subunit, yield isolated sodium currents of amplitudes greater than 4nA when studied in whole-cell configuration of the patch-clamp technique. The sodium currents are characterized by activation and inactivation properties similar to neuronal sodium channels, and are blocked by the voltage gated sodium channel blocker tetrodotoxin (TTX).

Baculovirus mediated high-level expression of luciferase in silkworm cells and larvae

Bombyx mori nuclear polyhedrosis virus (BmNPV)-based baculovirus expression system exploits silkworm larvae as an economical alternative to large-scale cell cultures for production of biomolecules. To generate recombinant BmNPV at high efficiency, we have achieved high efficiency transfection of B. mori cells, BmN, through lipofection. Optimal conditions for lipofection were standardized by quantification of the transient expression level of firefly luciferase (luc) reporter gene under control of an immediate early gene promoter of BmNPV Lipofection was 50-fold and 100-fold more efficient than the calcium phosphate method for transfecting BmN and Sf9 cells, respectively. Lipofection enabled us to generate a recombinant BmNPV (vBmluc), harboring luc under control of the strong polyhedrin promoter On infection with vBmluc, luciferase was expressed at very high levels, 170 mu g/10(6) BmN cells or 13 mg/larva. Expression of luciferase in vBmluc-infected larvae was visualized by luminescence emission instantaneously following luciferin injection generating ''glowing silkworms''.

H-DBUG: A High-level Debugging Framework for Protocol Verification using Assertions

The success of an ABV IP depends highly on the associated debugging environment. An efficient debugging environment helps the user to find out the exact location of the failure. Moreover, it provides information to the user in a refined detail of abstraction and permit adequate interaction. It has also been realized that adequate visualization support helps in tracking the behavioral aspects of the Design Under Test (DUT). Currently, the debugging tools provide information in the signal level and do not provide any information about the high-level behavior of the DUT. We present a debugging framework that takes the design specification, assertions and the user intent in a simple format and provides detailed information by processing the design trace on-line, or off-line. We also present a visualization framework to ease the debugging procedure. We have experimented with industrial standard on-chip bus protocols that ensure that this utility can be incorporated successfully in the present functional verification flow.

Iodide Retention by Modified Kaolinite in the Context of Safe Disposal of High Level Nuclear Waste

Bentonite clay is identified as potential buffer in deep geological repositories (DGR) that store high level radioactive wastes (HLW) as the expansive clay satisfies the expected mechanical and physicochemical functions of the buffer material. In the deep geological disposal of HLW, iodine-129 is one of the significant nuclides, attributable to its long half-life (half life 1⁄4 1:7 × 107 years). However, the negative charge on the basal surface of bentonite particles precludes retention of iodide anions. To render the bentonite effective in retaining hazardous iodide species in DGR, improvement of the anion retention capacity of bentonite becomes imperative. The iodide retention capac-ity of bentonite is improved by admixing 10 and 20% Ag-kaolinite (Ag-K) with bentonite (B) on a dry mass basis. The present study produced Ag-kaolinite by heating silver nitrate-kaolinite mixes at 400°C. Marginal release of iodide retained by Ag-kaolinite occurred under extreme acidic (pH 1⁄4 2:5) and alkaline (pH 1⁄4 12:5) conditions. The swell pressure and iodide etention results of the B-Ag-K specimens bring out that mixing Ag-K with bentonite does not chemically modify the expansive clay; the mixing is physical in nature and Ag-K presence only contributes to iodide retention of the admixture. DOI: 10.1061/(ASCE)HZ.2153-5515.0000121. © 2012 American Society of Civil Engineers.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have implemented a Firewall with this architecture in reconflgurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results in both speed and area improvement when it is implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields. High throughput classification invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly in terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for the worst case packet size. The Firewall rule update involves only memory re-initialization in software without any hardware change.

A Scalable High Throughput Firewall in FPGA

High end network security applications demand high speed operation and large rule set support. Packet classification is the core functionality that demands high throughput in such applications. This paper proposes a packet classification architecture to meet such high throughput. We have Implemented a Firewall with this architecture in reconfigurable hardware. We propose an extension to Distributed Crossproducting of Field Labels (DCFL) technique to achieve scalable and high performance architecture. The implemented Firewall takes advantage of inherent structure and redundancy of rule set by using, our DCFL Extended (DCFLE) algorithm. The use of DCFLE algorithm results In both speed and area Improvement when It is Implemented in hardware. Although we restrict ourselves to standard 5-tuple matching, the architecture supports additional fields.High throughput classification Invariably uses Ternary Content Addressable Memory (TCAM) for prefix matching, though TCAM fares poorly In terms of area and power efficiency. Use of TCAM for port range matching is expensive, as the range to prefix conversion results in large number of prefixes leading to storage inefficiency. Extended TCAM (ETCAM) is fast and the most storage efficient solution for range matching. We present for the first time a reconfigurable hardware Implementation of ETCAM. We have implemented our Firewall as an embedded system on Virtex-II Pro FPGA based platform, running Linux with the packet classification in hardware. The Firewall was tested in real time with 1 Gbps Ethernet link and 128 sample rules. The packet classification hardware uses a quarter of logic resources and slightly over one third of memory resources of XC2VP30 FPGA. It achieves a maximum classification throughput of 50 million packet/s corresponding to 16 Gbps link rate for file worst case packet size. The Firewall rule update Involves only memory re-initialiization in software without any hardware change.

Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures

In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations

Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) How much of instruction reuse is inherent in network processing applications?, (2) Can reuse be improved by reducing interference in the reuse buffer?, (3) What characteristics of network applications can be exploited to improve reuse?, and (4) What is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. "flows" with a low level microarchitectural feature of programs i.e. repetition of instructions and data along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.

Generalized Query-By-Rule: a heterogeneous database query language

This paper describes the design and implementation of a high-level query language called Generalized Query-By-Rule (GQBR) which supports retrieval, insertion, deletion and update operations. This language, based on the formalism of database logic, enables the users to access each database in a distributed heterogeneous environment, without having to learn all the different data manipulation languages. The compiler has been implemented on a DEC 1090 system in Pascal.