An ultra-stable Cu nanowire under thermo-mechanical loading: A molecular dynamic study

We report on the formation of a stable Body-Centered Heptahedral (BCH) crystalline nanobridge structure of diameter ~ 1nm under high strain rate tensile loading to a <100> Cu nanowire. Extensive Molecular Dynamics (MD) simulations are performed. Six different cross-sectional dimensions of Cu nanowires are analyzed, i.e. 0.3615 x 0.3615 nm2, 0.723 x 0.723 nm2, 1.0845 x 1.0845 nm2, 1.446 x 1.446 nm2, 1.8075 x 1.8075 nm2, and 2.169 x 2.169 nm2. The strain rates used in the present simulations are 1 x 109 s-1, 1 x 108 s-1, and 1 x 107 s-1. We have shown that the length of the nanobridge can be characterized by larger plastic strain. A large plastic deformation is an indication that the structure is highly stable. The BCH nanobridge structure also shows enhanced mechanical properties such as higher fracture toughness and higher failure strain. The effect of temperature, strain rate and size of the nanowire on the formation of BCH structure is also explained in details. We also show that the initial orientation of the nanowires play an important role on the formation of BCH crystalline structure. Results indicate that proper tailoring of temperature and strain rate during processing or in the device can lead to very long BCH nanobridge structure of Cu with enhanced mechanical properties, which may find potential application for nano-scale electronic circuits.

Maze solving automatons for self-healing of open interconnects: Modular add-on for circuit boards

We present the circuit board integration of a self-healing mechanism to repair open faults. The electric field driven mechanism physically restores fractured interconnects in electronic circuits and has the ability to solve mazes. The repair is performed by conductive particles dispersed in an insulating fluid. We demonstrate the integration of the healing module onto printed circuit boards and the ability of maze solving. We model and perform experiments on the influence of the geometry of conductive particles as well as the terminal impedances of the route on the healing efficiency. The typical heal rate is 10 mu m/s with healed route having mean resistance of 8 k Omega across a 200 micron gap and depending on the materials and concentrations used. (C) 2015 AIP Publishing LLC.

Impact of Energy Quantization on the Performance of Current-Biased SET Circuits

The current-biased single electron transistor (SET) (CBS) is an integral part of almost all hybrid CMOS SET circuits. In this paper, for the first time, the effects of energy quantization on the performance of CBS-based circuits are studied through analytical modeling and Monte Carlo simulations. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics, although it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: negative differential resistance (NDR) and neuron cell, which use the CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantizationmainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as ``quantization threshold'') that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studiedfor the current-biased negative differential resistance (NDR) circuitand hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.

Al/SiC carriers for microwave integrated circuits by a new technique of pressureless infiltration

Materials with high thermal conductivity and thermal expansion coefficient matching with that of Si or GaAs are being used for packaging high density microcircuits due to their ability of faster heat dissipation. Al/SiC is gaining wide acceptance as electronic packaging material due to the fact that its thermal expansion coefficient can be tailored to match with that of Si or GaAs by varying the Al:SiC ratio while maintaining the thermal conductivity more or less the same. In the present work, Al/SiC microwave integrated circuit (MIC) carriers have been fabricated by pressureless infiltration of Al-alloy into porous SiC preforms in air. This new technique provides a cheaper alternative to pressure infiltration or pressureless infiltration in nitrogen in producing Al/SiC composites for electronic packaging applications. Al-alloy/65vol% SiC composite exhibited a coefficient of thermal expansion of 7 x 10(-6) K-1 (25 degrees C-100 degrees C) and a thermal conductivity of 147 Wm(-1) K-1 at 30 degrees C. The hysteresis observed in thermal expansion coefficient of the composite in the temperature range 100 degrees C-400 degrees C has been attributed to the presence of thermal residual stresses in the composite. Thermal diffusivity of the composite measured over the temperature range from 30 degrees C to 400 degrees C showed a 55% decrease in thermal diffusivity with temperature. Such a large decrease in thermal diffusivity with temperature could be due to the presence of micropores, microcracks, and decohesion of the Al/SiC interfaces in the microstructure (all formed during cooling from the processing temperature). The carrier showed satisfactory performance after integrating it into a MIC.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Extrinsic Analog Synthesis using Piecewise Linear Current-Mode Circuits

A methodology is presented for the synthesis of analog circuits using piecewise linear (PWL) approximations. The function to be synthesized is divided into PWL segments such that each segment can be realized using elementary MOS current-mode programmable-gain circuits. A number of these elementary current-mode circuits when connected in parallel, it is possible to realize piecewise linear approximation of any arbitrary analog function with in the allowed approximation error bounds. Simulation results show a close agreement between the desired function and the synthesized output. The number of PWL segments used for approximation and hence the circuit area is determined by the required accuracy and the smoothness of the resulting function.

Editorial optical computing circuits, devices and systems

Information forms the basis of modern technology. To meet the ever-increasing demand for information, means have to be devised for a more efficient and better-equipped technology to intelligibly process data. Advances in photonics have made their impact on each of the four key applications in information processing, i.e., acquisition, transmission, storage and processing of information. The inherent advantages of ultrahigh bandwidth, high speed and low-loss transmission has already established fiber-optics as the backbone of communication technology. However, the optics to electronics inter-conversion at the transmitter and receiver ends severely limits both the speed and bit rate of lightwave communication systems. As the trend towards still faster and higher capacity systems continues, it has become increasingly necessary to perform more and more signal-processing operations in the optical domain itself, i.e., with all-optical components and devices that possess a high bandwidth and can perform parallel processing functions to eliminate the electronic bottleneck.

Operand Isolation Circuits with Reduced Overhead for Low Power Data-Path Design

Dynamic power dissipation due to redundant switching is an important metric in data-path design. This paper focuses on the use of ingenious operand isolation circuits for low power design. Operand isolation attempts to reduce switching by clamping or latching the output of a first level of combinational circuit. This paper presents a novel method using power supply switching wherein both PMOS and NMOS stacks of a circuit are connected to the same power supply. Thus, the output gets clamped or latched to the power supply value with minimal leakage. The proposed circuits make use of only two transistors to clamp the entire Multiple Input Multiple Output (MIMO) block. Also, the latch-based designs have higher drive strength in comparison to the existing methods. Simulation results have shown considerable area reduction in comparison to the existing techniques without increasing timing overhead.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Properties of the correlated electronic states of pyrene and hydrogenated pyrene

Approximate calculations are reported on pyrene within the PPP model Hamiltonian using a novel restricted CI scheme which employs both molecular orbital and valence bond techniques. Also reported are detailed full CI results of the PPP model on 2,7-dihydropyrene obtained using the valence bond method. Spectral studies, charge and spin density calculations in ground and excited states, and ring current calculations in the ground state of the molecules are presented. In pyrene, the calculated excitation energies are in good agreement with experiment. The closed structure pi-conjugated molecule pyrene appears to show smaller distortions from the ground state geometry compared with the open structure pi-conjugated molecule 2,7-dihydropyrene. The ground state equilibrium structure of 2,7-dihydropyrene can be viewed as two hexatriene molecules connected by a vinyl crosslink, as is evident from bond order and ring current calculations. This is consistent with the only Kekule resonant structure possible for this molecule.

Electronic Control of Facial Selection in Additions to Sterically Unbiased Ketones and Olefins

By definition, the two faces of a pi bond are equivalent.1 However, they are rendered nonequivalent in most molecules because of the absence of a plane of symmetry encompassing the double bond and the adjacent substituents. As a result, additions to trigonal centers from the two faces need not be equally facile. Exploiting this stereodifferentiation in a controlled manner represents one of the core problems in organic synthesis. Evidently, the factors which determine such diastereoselection need to be delineated in as much detail as possible.

Electronic Properties of the Vortex State in Cuprate Superconductors

The superconducting state of the cuprates in the presence of a magnetic field has been investigated very actively in the past few years through measurements of electrical and thermal transport, ac conductivity, specific heat, and other quantities. The observed behavior is not well understood; it probes the nature of quasiparticies, vortices, and their interactions in a superconductor with nodes in the pair amplitude. We summarize here experimental results and our attempts to understand the phenomena.