Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Counterclockwise exhumation of a hot orogen: The Paleoproterozoic ultrahigh-temperature granulites in the North China Craton

Regional metamorphic belts provide important constraints on the plate tectonic architecture of orogens. We report here a detailed petrologic examination of the sapphirine-bearing ultra-high temperature (UHT) granulites from the Jining Complex within the Khondalite Belt of the North China Craton (NCC). These granulites carry diagnostic UHT assemblages and their microstructures provide robust evidence to trace the prograde, peak and retrograde metamorphic evolution. The P–T conditions of the granulites estimated from XMgGrt(Mg/Fe + Mg) − XMgSpr isopleth calculations indicate temperature above 970 °C and pressures close to 7 kbar. We present phase diagrams based on thermodynamic computations to evaluate the mineral assemblages and microstructures and trace the metamorphic trajectory of the rocks. The evolution from Spl–Qtz–Ilm–Crd–Grt–Sil to Spr–Qtz–Crd–Opx–Ilm marks the prograde stage. The Spl–Qtz assemblage appears on the low-pressure side of the P–T space with Spr–Qtz stable at the high-pressure side, possibly representing an increase in pressure corresponding to compression. The spectacular development of sapphirine rims around spinel enclosed in quartz supports this inference. An evaluation of the key UHT assemblages based on model proportion calculation suggests a counterclockwise P–T path. With few exceptions, granulite-facies rocks developed along collisional metamorphic zones have generally been characterized by clockwise exhumation trajectories. Recent evaluation of the P–T paths of metamorphic rocks developed within collisional orogens indicates that in many cases the exhumation trajectories follow the model subduction geotherm, in accordance with a tectonic model in which the metamorphic rocks are subducted and exhumed along a plate boundary. The timing of UHT metamorphism in the NCC (c. 1.92 Ga) coincides with the assembly of the NCC within the Paleoproterozoic Columbia supercontinent, a process that would have involved subduction of passive margins sediments and closure of the intervening ocean. Thus, the counterclockwise P–T path obtained in this study correlates well with a tectonic model involving subduction and final collisional suturing, with the UHT granulites representing the core of the hot or ultra-hot orogen developed during Columbia amalgamation.

On trade-off solution pairs in a special type of transportation problem

Abstract is not available.

Exploring energy-performance trade-offs for heterogeneous interconnect clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving clock speed, reducing energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires which leads to delay in execution and significantly high energy consumption.In this paper, we propose a new instruction scheduling algorithm that exploits scheduling slacks of instructions and communication slacks of data values together to achieve better energy-performance trade-offs for clustered architectures with heterogeneous interconnect. Our instruction scheduling algorithm achieves 35% and 40% reduction in communication energy, whereas the overall energy-delay product improves by 4.5% and 6.5% respectively for 2 cluster and 4 cluster machines with marginal increase (1.6% and 1.1%) in execution time. Our test bed uses the Trimaran compiler infrastructure.

The Relay Selection and Transmission Trade-off in Cooperative Communication Systems

A common and practical paradigm in cooperative communication systems is the use of a dynamically selected `best' relay to decode and forward information from a source to a destination. Such systems use two phases - a relay selection phase, in which the system uses transmission time and energy to select the best relay, and a data transmission phase, in which it uses the spatial diversity benefits of selection to transmit data. In this paper, we derive closed-form expressions for the overall throughput and energy consumption, and study the time and energy trade-off between the selection and data transmission phases. To this end, we analyze a baseline non-adaptive system and several adaptive systems that adapt the selection phase, relay transmission power, or transmission time. Our results show that while selection yields significant benefits, the selection phase's time and energy overhead can be significant. In fact, at the optimal point, the selection can be far from perfect, and depends on the number of relays and the mode of adaptation. The results also provide guidelines about the optimal system operating point for different modes of adaptation. The analysis also sheds new insights on the fast splitting-based algorithm considered in this paper for relay selection.

The role of sustainable agriculture and renewable-resource management in reducing greenhouse-gas emissions and increasing sinks in China and India

This paper contains an analysis of the technical options in agriculture for reducing greenhouse-gas emissions and increasing sinks, arising from three distinct mechanisms: (i) increasing carbon sinks in soil organic matter and above-ground biomass; (ii) avoiding carbon emissions from farms by reducing direct and indirect energy use; and (iii) increasing renewable-energy production from biomass that either substitutes for consumption of fossil fuels or replaces inefficient burning of fuelwood or crop residues, and so avoids carbon emissions, together with use of biogas digesters and improved cookstoves. We then review best-practice sustainable agriculture and renewable-resource-management projects and initiatives in China and India, and analyse the annual net sinks being created by these projects, and the potential market value of the carbon sequestered. We conclude with a summary of the policy and institutional conditions and reforms required for adoption of best sustainability practice in the agricultural sector to achieve the desired reductions in emissions and increases in sinks. A review of 40 sustainable agriculture and renewable-resource-management projects in China and India under the three mechanisms estimated a carbon mitigation potential of 64.8 MtC yr(-1) from 5.5 Mha. The potential income for carbon mitigation is $324 million at $5 per tonne of carbon. The potential exists to increase this by orders of magnitude, and so contribute significantly to greenhouse-gas abatement. Most agricultural mitigation options also provide several ancillary benefits. However, there are many technical, financial, policy, legal and institutional barriers to overcome.

A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Trade determination in multi-attribute exchanges

Electronic exchanges are double-sided marketplaces that allow multiple buyers to trade with multiple sellers, with aggregation of demand and supply across the bids to maximize the revenue in the market. Two important issues in the design of exchanges are (1) trade determination (determining the number of goods traded between any buyer-seller pair) and (2) pricing. In this paper we address the trade determination issue for one-shot, multi-attribute exchanges that trade multiple units of the same good. The bids are configurable with separable additive price functions over the attributes and each function is continuous and piecewise linear. We model trade determination as mixed integer programming problems for different possible bid structures and show that even in two-attribute exchanges, trade determination is NP-hard for certain bid structures. We also make some observations on the pricing issues that are closely related to the mixed integer formulations.

Performance and variability trade-off with gate-to-source/drain overlap length

The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Diversity-Rate Trade-off for Fading Channels with Power Control

We consider a complex, additive, white Gaussian noise channel with flat fading. We study its diversity order vs transmission rate for some known power allocation schemes. The capacity region is divided into three regions. For one power allocation scheme, the diversity order is exponential throughout the capacity region. For selective channel inversion (SCI) scheme, the diversity order is exponential in low and high rate region but polynomial in mid rate region. For fast fading case we also provide a new upper bound on block error probability and a power allocation scheme that minimizes it. The diversity order behaviour of this scheme is same as for SCI but provides lower BER than the other policies.

Threats and trade-fffs in resource critical crowdsourcing tasks over networks

In recent times, crowdsourcing over social networks has emerged as an active tool for complex task execution. In this paper, we address the problem faced by a planner to incen-tivize agents in the network to execute a task and also help in recruiting other agents for this purpose. We study this mecha-nism design problem under two natural resource optimization settings: (1) cost critical tasks, where the planner’s goal is to minimize the total cost, and (2) time critical tasks, where the goal is to minimize the total time elapsed before the task is executed. We define a set of fairness properties that should beideally satisfied by a crowdsourcing mechanism. We prove that no mechanism can satisfy all these properties simultane-ously. We relax some of these properties and define their ap-proximate counterparts. Under appropriate approximate fair-ness criteria, we obtain a non-trivial family of payment mech-anisms. Moreover, we provide precise characterizations of cost critical and time critical mechanisms.

Regenerating codes: A reformulated storage-bandwidth trade-off and a new construction

In this paper, the storage-repair-bandwidth (SRB) trade-off curve of regenerating codes is reformulated to yield a tradeoff between two global parameters of practical relevance, namely information rate and repair rate. The new information-repair-rate (IRR) tradeoff provides a different and insightful perspective on regenerating codes. For example, it provides a new motivation for seeking to investigate constructions corresponding to the interior of the SRB tradeoff. Interestingly, each point on the SRB tradeoff corresponds to a curve in the IRR tradeoff setup. We characterize completely, functional repair under the IRR framework, while for exact repair, an achievable region is presented. In the second part of this paper, a rate-half regenerating code for the minimum storage regenerating point is constructed that draws upon the theory of invariant subspaces. While the parameters of this rate-half code are the same as those of the MISER code, the construction itself is quite different.