35 resultados para AMPLIFIER

em Indian Institute of Science - Bangalore - Índia


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Negative impedance converters (NIC's) may be used to realize negative driving-point impedances. The effect of the nonideal characteristics of the operational amplifier such as finite frequencydependent gain and output impedance on the performance of the negative impedances is analyzed. Detailed equivalent circuits showing the additional positive or negative inductive impedances due to the nonideal characteristics are given for negative resistance and negative capacitance realizations, and their relative performances are compared. The experimental results confirm the validity of the equivalent circuits. The effect of the slew rate of the operational amplifier on the maximum signal-handling capability (SHC) of the negative impedances at high frequencies is studied. Practical design considerations for achieving wider bandwidth as well as improved SHC are discussed.

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A finite gain differential amplifier is used along with a few passive RC elements to simulate an inductor. Methods for obtaining low Q inductance and frequency dependent high QI inductance are described. Sensitivity analysis when the gain varies is also included.

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The deviation in the performance of active networks due to practical operational amplifiers (OA) is mainly because of the finite gain bandwidth productBand nonzero output resistanceR_0. The effect ofBandR_0on two OA impedances and single and multi-OA filters are discussed. In filters, the effect ofR_0is to add zeros to the transfer function often making it nonminimum phase. A simple method of analysis has been suggested for 3-OA biquad and coupled biquad circuits. A general method of noise minimization of the generalized impedance converter (GIC), while operating OA's within the prescribed voltage and current limits, is also discussed. The 3-OA biquadratic sections analyzed also exhibit noise behavior and signal handling capacity similar to the GIC. The GIC based structures are found to be better than other configurations both in biquadratic sections and direct realizations of higher order transfer functions.

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In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz. High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.

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It has been shown that the conventional practice of designing a compensated hot wire amplifier with a fixed ceiling to floor ratio results in considerable and unnecessary increase in noise level at compensation settings other than optimum (which is at the maximum compensation at the highest frequency of interest). The optimum ceiling to floor ratio has been estimated to be between 1.5-2.0 ωmaxM. Application of the above considerations to an amplifier in which the ceiling to floor ratio is optimized at each compensation setting (for a given amplifier band-width), shows the usefulness of the method in improving the signal to noise ratio.

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Chronic recording of neural signals is indispensable in designing efficient brain–machine interfaces and to elucidate human neurophysiology. The advent of multichannel micro-electrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system can vary over time due to change in electrode–neuron distance and background noise. We propose a neural amplifier in UMC 130 nm, 1P8M complementary metal–oxide–semiconductor (CMOS) technology. It can be biased adaptively from 200 nA to 2 $mu{rm A}$, modulating input referred noise from 9.92 $mu{rm V}$ to 3.9 $mu{rm V}$. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. Optimum sizing of the input transistors minimizes the accentuation of the input referred noise of the amplifier and obviates the need of large input capacitance. The amplifier achieves a noise efficiency factor of 2.58. The amplifier can pass signal from 5 Hz to 7 kHz and the bandwidth of the amplifier can be tuned for rejecting low field potentials (LFP) and power line interference. The amplifier achieves a mid-band voltage gain of 37 dB. In vitro experiments are performed to validate the applicability of the neural low noise amplifier in neural recording systems.

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The design of a three‐stage high‐gain amplifier for laboratory use in audiofrequency investigations is described. Four‐electrode tubes are used as screen‐grid amplifiers and an amplification of the order of 200 per stage is obtained. The inaccuracy of McDonald's formula for calculation of stage‐gain has been pointed out. The gain‐frequency characteristics are given for power as well as voltage amplification. It is shown that extreme care is necessary in the design of shielding to obtain high‐voltage amplification of the order of 120 decibels as obtained in this three‐stage amplifier.

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This paper reports the fabrication and characterization of an ultrafast laser written Er-doped chalcogenide glass buried waveguide amplifier; Er-doped GeGaS glass has been synthesized by the vacuum sealed melt quenching technique. Waveguides have been fabricated inside the 4 mm long sample by direct ultrafast laser writing. The total passive fiber-to-fiber insertion loss is 2.58 +/- 0.02 dB at 1600 nm, including a propagation loss of 1.6 +/- 0.3 dB. Active characterization shows a relative gain of 2.524 +/- 0.002 dB/cm and 1.359 +/- 0.005 dB/cm at 1541 nm and 1550 nm respectively, for a pump power of 500 mW at a wavelength of 980 nm. (C) 2012 Optical Society of America

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Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

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A monolithic surface acoustic wave (SAW) resonator operating at 156 MHz, in which the frequency controlling element is a Fabry–Perot type of SAW resonator and the gain element is a monolithic SAW amplifier (SiOx/InSb/SiOx structure located inside the SAW resonator cavity) is described and experimental details presented. Based on the existing experimental data, an uhf monolithic ring resonator oscillator is proposed. Journal of Applied Physics is copyrighted by The American Institute of Physics.

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A monolithic surface acoustic wave (SAW) resonator operating at 156 MHz, in which the frequency controlling element is a Fabry–Perot type of SAW resonator and the gain element is a monolithic SAW amplifier (SiOx/InSb/SiOx structure located inside the SAW resonator cavity) is described and experimental details presented. Based on the existing experimental data, an uhf monolithic ring resonator oscillator is proposed. Journal of Applied Physics is copyrighted by The American Institute of Physics.

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The implementation of three-phase sinusoidal pulse-width-modulated inverter control strategy using microprocessor is discussed in this paper. To save CPU time, the DMA technique is used for transferring the switching pattern from memory to the pulse amplifier and isolation circuits of individual thyristors in the inverter bridge. The method of controlling both voltage and frequency is discussed here.

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The implementation of three-phase sinusoidal pulse-width-modulated inverter control strategy using microprocessor is discussed in this paper. To save CPU time, the DMA technique is used for transferring the switching pattern from memory to the pulse amplifier and isolation circuits of individual thyristors in the inverter bridge. The method of controlling both voltage and frequency is discussed here.