A 100MHz to 1GHz, 0.35V to 1.5V supply 256 x 64 SRAM mock using symmetrized 9T SRAM cell with controlled read

In this paper, we present Dynamic Voltage and Frequency Managed 256 x 64 SRAM block in 65nm technology, for frequency ranging from 100MHz to 1GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose Static Noise Margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and Hold Noise Margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag-super-cut-off in stand-by mode without affecting its performance in active mode of operation. The Read Bit Line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read

In this paper, we present dynamic voltage and frequency Managed 256 x 64 SRAM block in 65 nm technology, for frequency ranging from 100 MHz to 1 GHz. The total energy is minimized for any operating frequency in the above range and leakage energy is minimized during standby mode. Since noise margin of SRAM cell deteriorates at low voltages, we propose static noise margin improvement circuitry, which symmetrizes the SRAM cell by controlling the body bias of pull down NMOS transistor. We used a 9T SRAM cell that isolates Read and hold noise margin and has less leakage. We have implemented an efficient technique of pushing address decoder into zigzag- super-cut-off in stand-by mode without affecting its performance in active mode of operation. The read bit line (RBL) voltage drop is controlled and pre-charge of bit lines is done only when needed for reducing power wastage.

Design of a Low Power 64 Point FFT Architecture for WLAN Applications

This paper presents a Radix-4(3) based FFT architecture suitable for OFDM based WLAN applications. The radix-4(3) parallel unrolled architecture presented here, uses a radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. A 64 point FFT processor based on the proposed architecture has been implemented in UMC 130nm 1P8M CMOS process with a maximum clock frequency of 100 MHz and area of 0.83mm(2). The proposed processor provides a throughput of four times the clock rate and can finish one 64 point FFT computation in 16 clock cycles. For IEEE 802.11a/g WLAN, the processor needs to be operated at a clock rate of 5 MHz with a power consumption of 2.27 mW which is 27% less than the previously reported low power implementations.

Detailed mechanism and kinetic study of CO oxidation on cobalt oxide surfaces

Co3O4 catalysts were prepared by combustion synthesis using different fuels glycine (G), ODH (O) and urea (U). Morphological changes of the materials were observed by using different fuels. The prepared catalysts were characterized by XRD, XPS, SEM, TEM, BET and DRIFTS analysis. All compounds showed 100% conversion of CO below 175C. The prepared catalysts exhibited very high stability and conversions did not decrease even after 50 h of continuous operation. The oxygen storage capacity (OSC) of materials was measured by H-2-TPR analysis. Co3O4-O is having high OSC among the synthesized catalysts. The activation energies of these catalysts were found to be in the range of 42.3-64.8 kJ mol(-1). With DRIFTS analysis, the surface carbonates, superoxide anions, adsorbed CO, O-2 species on the catalyst surface were found and this information was used to develop a detailed reaction pathway. A kinetic model was developed with the help of proposed mechanism and used to fit the data. (C) 2014 Elsevier B.V. All rights reserved.

Probing the role of highly conserved residues in triosephosphate isomerase-analysis of site specific mutants at positions 64 and 75 in the Plasmodial enzyme

Highly conserved residues in enzymes are often found to be clustered close to active sites, suggesting that functional constraints dictate the nature of amino acid residues accommodated at these sites. Using the Plasmodiumfalciparum triosephosphate isomerase (PfTIM) enzyme () as a template, we have examined the effects of mutations at positions 64 and 75, which are not directly involved in the proton transfer cycle. Thr (T) occurring at position 75 is completely conserved, whereas only Gln (Q) and Glu (E) are accommodated at position 64. Biophysical and kinetic data are reported for four T75 (T75S/V/C/N) and two Q64 (Q64N/E) mutants. The dimeric structure is weakened in the Q64E and Q64N mutants, whereas dimer integrity is unimpaired in all four T75 mutants. Measurement of the concentration dependence of enzyme activity permits an estimate of K-d values for dimer dissociation (Q64N=73.79.2nm and Q64E=44.6 +/- 8.4nm). The T75S/V/C mutants have activities comparable to the wild-type enzyme, whereas a fourfold drop is observed for T75N. All four T75 mutants show a dramatic fall in activity between 35 degrees C and 45 degrees C. Crystal structure determination of the T75S/V/N mutants provides insights into the variations in local interactions, with the T75N mutant showing the largest changes. Hydrogen-bond interactions determine dimer stability restricting the choice of residues at position 64 to Gln (Q) and Glu (E). At position 75, the overwhelming preference for Thr (T) may be dictated by the imperative of maintaining temperature stability of enzyme activity.