134 resultados para Hardware Transactional Memory


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Introduction: Immunomodulators are agents, which can modulate the immune response to specific antigens, while causing least toxicity to the host system. Being part of the modern vaccine formulations, these compounds have contributed remarkably to the field of therapeutics. Despite the successful record maintained by these agents, the requirement of novel immunomodulators keeps increasing due to the increasing severity of diseases. Hence, research regarding the same holds great importance. Areas covered: In this review, we discuss the role of immunomodulators in improving performance of various vaccines used for counteracting most threatening infectious diseases, mechanisms behind their action and criteria for development of novel immunomodulators. Expert opinion: Understanding the molecular mechanisms underlying immune response is a prerequisite for development of effective therapeutics as these are often exploited by pathogens for their own propagation. Keeping this in mind, the present research in the field of immunotherapy focuses on developing immunomodulators that would not only enhance the protection against pathogen, but also generate a long-term memory response. With the introduction of advanced formulations including combination of different kinds of immunomodulators, one can expect tremendous success in near future.

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Investigations on the electrical switching, structural, optical and photoacoustic analysis have been undertaken on chalcogenide GeSe1.5S0.5 thin films of various thicknesses prepared by vacuum evaporation technique. The decrease of band gap energy with increase in film thickness has been explained using the `density of states model'. The structural units of the films are characterized using Raman spectroscopy and the deconvoluted Raman peaks obtained from Gaussian fit around 188 cm(-1), 204 cm(-1) and 214 cm(-1) favors Ge-chalcogen tetrahedral units forming corner and edge sharing tetrahedra. All the thin films samples have been exhibited memory-type electrical switching behavior. An enhancement in the threshold voltages of GeSe1.5S0.5 thin films have been observed with increase in film thickness. The thickness dependence of switching voltages provide an insight into the switching mechanism and it is explained by the Joule heating effect. (C) 2014 Elsevier B.V. All rights reserved.

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As rapid brain development occurs during the neonatal period, environmental manipulation during this period may have a significant impact on sleep and memory functions. Moreover, rapid eye movement (REM) sleep plays an important role in integrating new information with the previously stored emotional experience. Hence, the impact of early maternal separation and isolation stress (MS) during the stress hyporesponsive period (SHRP) on fear memory retention and sleep in rats were studied. The neonatal rats were subjected to maternal separation and isolation stress during postnatal days 5-7 (6 h daily/3 d). Polysomnographic recordings and differential fear conditioning was carried out in two different sets of rats aged 2 months. The neuronal replay during REM sleep was analyzed using different parameters. MS rats showed increased time in REM stage and total sleep period also increased. MS rats showed fear generalization with increased fear memory retention than normal control (NC). The detailed analysis of the local field potentials across different time periods of REM sleep showed increased theta oscillations in the hippocampus, amygdala and cortical circuits. Our findings suggest that stress during SHRP has sensitized the hippocampus amygdala cortical loops which could be due to increased release of corticosterone that generally occurs during REM sleep. These rats when subjected to fear conditioning exhibit increased fear memory and increased, fear generalization. The development of helplessness, anxiety and sleep changes in human patients, thus, could be related to the reduced thermal, tactile and social stimulation during SHRP on brain plasticity and fear memory functions. (C) 2014 Elsevier B.V. All rights reserved.

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A Field Programmable Gate Array (FPGA) based hardware accelerator for multi-conductor parasitic capacitance extraction, using Method of Moments (MoM), is presented in this paper. Due to the prohibitive cost of solving a dense algebraic system formed by MoM, linear complexity fast solver algorithms have been developed in the past to expedite the matrix-vector product computation in a Krylov sub-space based iterative solver framework. However, as the number of conductors in a system increases leading to a corresponding increase in the number of right-hand-side (RHS) vectors, the computational cost for multiple matrix-vector products present a time bottleneck, especially for ill-conditioned system matrices. In this work, an FPGA based hardware implementation is proposed to parallelize the iterative matrix solution for multiple RHS vectors in a low-rank compression based fast solver scheme. The method is applied to accelerate electrostatic parasitic capacitance extraction of multiple conductors in a Ball Grid Array (BGA) package. Speed-ups up to 13x over equivalent software implementation on an Intel Core i5 processor for dense matrix-vector products and 12x for QR compressed matrix-vector products is achieved using a Virtex-6 XC6VLX240T FPGA on Xilinx's ML605 board.

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Modulus variation of NiTi shape memory alloy has been investigated at microstructural level through nano dynamical mechanical analysis and compared with bulk experimental measurements. The differences between the modulus values at the macro and micro level as well as within the micro level are discussed and the corresponding variations have been explained based on the crystal structure, orientation and misorientation. The experimental results confirm a higher modulus value for the martensite phase that is in agreement with the theoretical predictions. (C) 2015 Elsevier B. V. All rights reserved.

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This paper presents a low energy memory decoder architecture for ultra-low-voltage systems containing multiple voltage domains. Due to limitations in scalability of memory supply voltages, these systems typically contain a core operating at subthreshold voltages and memories operating at a higher voltage. This difference in voltage provides a timing slack on the memory path as the core supply is scaled. The paper analyzes the feasibility and trade-offs in utilizing this timing slack to operate a greater section of memory decoder circuitry at the lower supply. A 256x16-bit SRAM interface has been designed in UMC 65nm low-leakage process to evaluate the above technique with the core and memory operating at 280 mV and 500 mV respectively. The technique provides a reduction of up to 20% in energy/cycle of the row decoder without any penalty in area and system-delay.

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Interfacial properties of Shape Memory Alloy (SMA) reinforced polymer matrix composites can be enhanced by improving the interfacial bonding. This paper focuses on studying the interfacial stresses developed in the SMA-epoxy interface due to various laser shot penning conditions. Fiber-pull test-setup is designed to understand the role of mechanical bias stress cycling and thermal actuation cycling. Phase transformation is tracked over mechanical and thermal fatigue cycles. A micromechanics based model developed earlier based on shear lag in SMA and energy based consistent homogenization is extended here to incorporate the stress-temperature phase diagram parameters for modeling fatigue.

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Branch divergence is a very commonly occurring performance problem in GPGPU in which the execution of diverging branches is serialized to execute only one control flow path at a time. Existing hardware mechanism to reconverge threads using a stack causes duplicate execution of code for unstructured control flow graphs. Also the stack mechanism cannot effectively utilize the available parallelism among diverging branches. Further, the amount of nested divergence allowed is also limited by depth of the branch divergence stack. In this paper we propose a simple and elegant transformation to handle all of the above mentioned problems. The transformation converts an unstructured CFG to a structured CFG without duplicating user code. It incurs only a linear increase in the number of basic blocks and also the number of instructions. Our solution linearizes the CFG using a predicate variable. This mechanism reconverges the divergent threads as early as possible. It also reduces the depth of the reconvergence stack. The available parallelism in nested branches can be effectively extracted by scheduling the basic blocks to reduce the effect of stalls due to memory accesses. It can also increase execution efficiency of nested loops with different trip counts for different threads. We implemented the proposed transformation at PTX level using the Ocelot compiler infrastructure. We evaluated the technique using various benchmarks to show that it can be effective in handling the performance problem due to divergence in unstructured CFGs.

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In this paper, we propose a H.264/AVC compressed domain human action recognition system with projection based metacognitive learning classifier (PBL-McRBFN). The features are extracted from the quantization parameters and the motion vectors of the compressed video stream for a time window and used as input to the classifier. Since compressed domain analysis is done with noisy, sparse compression parameters, it is a huge challenge to achieve performance comparable to pixel domain analysis. On the positive side, compressed domain allows rapid analysis of videos compared to pixel level analysis. The classification results are analyzed for different values of Group of Pictures (GOP) parameter, time window including full videos. The functional relationship between the features and action labels are established using PBL-McRBFN with a cognitive and meta-cognitive component. The cognitive component is a radial basis function, while the meta-cognitive component employs self-regulation to achieve better performance in subject independent action recognition task. The proposed approach is faster and shows comparable performance with respect to the state-of-the-art pixel domain counterparts. It employs partial decoding, which rules out the complexity of full decoding, and minimizes computational load and memory usage. This results in reduced hardware utilization and increased speed of classification. The results are compared with two benchmark datasets and show more than 90% accuracy using the PBL-McRBFN. The performance for various GOP parameters and group of frames are obtained with twenty random trials and compared with other well-known classifiers in machine learning literature. (C) 2015 Elsevier B.V. All rights reserved.

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Coarse Grained Reconfigurable Architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi- core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.

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This paper discusses a novel high-speed approach for human action recognition in H.264/AVC compressed domain. The proposed algorithm utilizes cues from quantization parameters and motion vectors extracted from the compressed video sequence for feature extraction and further classification using Support Vector Machines (SVM). The ultimate goal of the proposed work is to portray a much faster algorithm than pixel domain counterparts, with comparable accuracy, utilizing only the sparse information from compressed video. Partial decoding rules out the complexity of full decoding, and minimizes computational load and memory usage, which can result in reduced hardware utilization and faster recognition results. The proposed approach can handle illumination changes, scale, and appearance variations, and is robust to outdoor as well as indoor testing scenarios. We have evaluated the performance of the proposed method on two benchmark action datasets and achieved more than 85 % accuracy. The proposed algorithm classifies actions with speed (> 2,000 fps) approximately 100 times faster than existing state-of-the-art pixel-domain algorithms.

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Thin films of different thicknesses in the range of 200-720 nm have been deposited on glass substrates at room temperature using thermal evaporation technique. The structural investigations revealed that the as-deposited films are amorphous in nature. The surface roughness of the films shows an increasing trend at higher thickness of the films. The surface roughness of the films shows an increasing trend at higher thickness of the films. Interference fringes in the transmission spectra of these films suggest that the films are fairly smooth and uniform. The optical absorption in Sb2Se3 film is described using indirect transition and the variation in band gaps is explained on the basis of defects and disorders in the chalcogenide systems. Raman spectrum confirms the increase of orderliness with film thickness. From the I-V characteristics, a memory type switching is observed whose threshold voltage increases with film thickness. (C) 2015 Elsevier B.V. All rights reserved.

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Quantum cellular automata (QCA) is a new technology in the nanometer scale and has been considered as one of the alternative to CMOS technology. In this paper, we describe the design and layout of a serial memory and parallel memory, showing the layout of individual memory cells. Assuming that we can fabricate cells which are separated by 10nm, memory capacities of over 1.6 Gbit/cm2 can be achieved. Simulations on the proposed memories were carried out using QCADesigner, a layout and simulation tool for QCA. During the design, we have tried to reduce the number of cells as well as to reduce the area which is found to be 86.16sq mm and 0.12 nm2 area with the QCA based memory cell. We have also achieved an increase in efficiency by 40%.These circuits are the building block of nano processors and provide us to understand the nano devices of the future.

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We demonstrate all inorganic, robust, cost-effective, spin-coated, two-terminal capacitive memory metal-oxide nanoparticle-oxide-semiconductor devices with cadmium telluride nanoparticles sandwiched between aluminum oxide phosphate layers to form the dielectric memory stack. Using a novel high-speed circuit to decouple reading and writing, experimentally measured memory windows, programming voltages, retention times, and endurance are comparable with or better than the two-terminal memory devices realized using other fabrication techniques.