Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Large external memory bandwidth requirement leads to increased system power dissipation and cost in video coding application. Majority of the external memory traffic in video encoder is due to reference data accesses. We describe a lossy reference frame compression technique that can be used in video coding with minimal impact on quality while significantly reducing power and bandwidth requirement. The low cost transformless compression technique uses lossy reference for motion estimation to reduce memory traffic, and lossless reference for motion compensation (MC) to avoid drift. Thus, it is compatible with all existing video standards. We calculate the quantization error bound and show that by storing quantization error separately, bandwidth overhead due to MC can be reduced significantly. The technique meets key requirements specific to the video encode application. 24-39% reduction in peak bandwidth and 23-31% reduction in total average power consumption are observed for IBBP sequences.

Test Application Time Minimization for RAS using Basis Optimization of Column Decoder

Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.

Hierarchies of circuit classes that are closed under complement

We examine three hierarchies of circuit classes and show they are closed under complementation. (1) The class of languages recognized by a family of polynomial size skew circuits with width O(w), are closed under complement. (2) The class of languages recognized by family of polynomial size circuits with width O(w) and polynomial tree-size, are closed under complement. (3) The class of languages recognized by a family of polynomial size, O(log(n)) depth, bounded AND fan-in with OR fan-in f (f⩾log(n)) circuits are closed under complement. These improve upon the results of (i) Immerman (1988) and Szelepcsenyi (1988), who show that 𝒩L𝒪𝒢 is closed under complementation, and (ii) Borodin et al. (1989), who show that L𝒪𝒢𝒞ℱL is closed under complement

On generating optimal signal probabilities for random tests: A genetic approach

Genetic Algorithms are robust search and optimization techniques. A Genetic Algorithm based approach for determining the optimal input distributions for generating random test vectors is proposed in the paper. A cost function based on the COP testability measure for determining the efficacy of the input distributions is discussed, A brief overview of Genetic Algorithms (GAs) and the specific details of our implementation are described. Experimental results based on ISCAS-85 benchmark circuits are presented. The performance pf our GA-based approach is compared with previous results. While the GA generates more efficient input distributions than the previous methods which are based on gradient descent search, the overheads of the GA in computing the input distributions are larger. To account for the relatively quick convergence of the gradient descent methods, we analyze the landscape of the COP-based cost function. We prove that the cost function is unimodal in the search space. This feature makes the cost function amenable to optimization by gradient-descent techniques as compared to random search methods such as Genetic Algorithms.

Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology

Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

Link failure detection for maintaining session continuity in packet data networks

A link failure in the path of a virtual circuit in a packet data network will lead to premature disconnection of the circuit by the end-points. A soft failure will result in degraded throughput over the virtual circuit. If these failures can be detected quickly and reliably, then appropriate rerouteing strategies can automatically reroute the virtual circuits that use the failed facility. In this paper, we develop a methodology for analysing and designing failure detection schemes for digital facilities. Based on errored second data, we develop a Markov model for the error and failure behaviour of a T1 trunk. The performance of a detection scheme is characterized by its false alarm probability and the detection delay. Using the Markov model, we analyse the performance of detection schemes that use physical layer or link layer information. The schemes basically rely upon detecting the occurrence of severely errored seconds (SESs). A failure is declared when a counter, that is driven by the occurrence of SESs, reaches a certain threshold.For hard failures, the design problem reduces to a proper choice;of the threshold at which failure is declared, and on the connection reattempt parameters of the virtual circuit end-point session recovery procedures. For soft failures, the performance of a detection scheme depends, in addition, on how long and how frequent the error bursts are in a given failure mode. We also propose and analyse a novel Level 2 detection scheme that relies only upon anomalies observable at Level 2, i.e. CRC failures and idle-fill flag errors. Our results suggest that Level 2 schemes that perform as well as Level 1 schemes are possible.

Petri net-based modeling of a class of complex digital systems

We present through the use of Petri Nets, modeling techniques for digital systems realizable using FPGAs. These Petri Net models are used for logic validation at the logic design phase. The technique is illustrated by modeling practical circuits. Further, the utility of the technique with respect to timing analysis of the modeled digital systems is considered. Copyright (C) 1997 Elsevier Science Ltd

Analysis, Design, Modeling, and Implementation of an Active Clamp HF Link Converter

This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.

Combinatorial logic synthesis using technology directed decomposition

The aim of logic synthesis is to produce circuits which satisfy the given boolean function while meeting timing constraints and requiring the minimum silicon area. Logic synthesis involves two steps namely logic decomposition and technology mapping. Existing methods treat the two as separate operation. The traditional approach is to minimize the number of literals without considering the target technology during the decomposition phase. The decomposed expressions are then mapped on to the target technology to optimize the area, Timing optimization is carried out subsequently, A new approach which treats logic decomposition and technology maping as a single operation is presented. The logic decomposition is based on the parameters of the target technology. The area and timing optimization is carried out during logic decomposition phase itself. Results using MCNC circuits are presented to show that this method produces circuits which are 38% faster while requiring 14% increase in area.

Ellipsometry as a Sensitive Technique to Probe film -Substrate Interfaces: Al2O3 on Si(100)

An attempt has been made to study the film-substrate interface by using a sensitive, non- conventional tool. Because of the prospective use of gate oxide in MOSFET devices, we have chosen to study alumina films grown on silicon. Film-substrate interface of alumina grown by MOCVD on Si(100) was studied systematically using spectroscopic ellipsometry in the range 1.5-5.0 eV, supported by cross-sectional SEM, and SIMS. The (ε1,ε2) versus energy data obtained for films grown at 600°C, 700°C, and 750°C were modeled to fit a substrate/interface/film “sandwich”. The experimental results reveal (as may be expected) that the nature of the substrate -film interface depends strongly on the growth temperature. The simulated (ε1,ε2) patterns are in excellent agreement with observed ellipsometric data. The MOCVD precursors results the presence of carbon in the films. Theoretical simulation was able to account for the ellipsometry data by invoking the presence of “free” carbon in the alumina films.

Electron Cyclotron Resonance in Strained Si and Si0.94Ge0.06 Channels on Relaxed Si0.62Ge0.38 Buffers Grown by Rapid Thermal Chemical Vapor Deposition

We report the far-infrared measurements of the electron cyclotron resonance absorption in n-type Si/Si0. 62Ge0.38 and Si0.94Ge0.06 /Si0. 62Ge0.38 modulation- doped heterostructures grown by rapid thermal chemical vapor deposition. The strained Si and Si0.94Ge0.06 channels were grown on relaxed Si0.62Ge0.38 buffer layers, which consist of 0.6 μm uniform Si0.62Ge0.38 layers and 0.5 μm compositionally graded relaxed SiGe layers from 0% Ge to 38 % Ge. The buffer layers were annealed at 800 °C for 1 hr to obtain complete relaxation. The samples had 100 Å spacers and 300 Å 2×1019 cm-3 n-type supply layers on the tops of the 75 Å channels. The far-infrared measurements of electron cyclotron resonance were performed at 4K with the magnetic field of 4 – 8 Tesla. The effective masses determined from the slope of center frequency of absorption peak vs applied magnetic field plot are 0.20 mo and 0.19 mo for the two dimensional electron gases in the Si and Si0.94Ge0.06 channels, respectively. The Si effective mass is very close to that of two dimensional electron gas in Si MOSFET (0.198mo). The electron effective mass of Si0.94Ge0.06 is reported for the first time and about 5 % lower than that of pure Si.

An ultra-stable Cu nanowire under thermo-mechanical loading: A molecular dynamic study

We report on the formation of a stable Body-Centered Heptahedral (BCH) crystalline nanobridge structure of diameter ~ 1nm under high strain rate tensile loading to a <100> Cu nanowire. Extensive Molecular Dynamics (MD) simulations are performed. Six different cross-sectional dimensions of Cu nanowires are analyzed, i.e. 0.3615 x 0.3615 nm2, 0.723 x 0.723 nm2, 1.0845 x 1.0845 nm2, 1.446 x 1.446 nm2, 1.8075 x 1.8075 nm2, and 2.169 x 2.169 nm2. The strain rates used in the present simulations are 1 x 109 s-1, 1 x 108 s-1, and 1 x 107 s-1. We have shown that the length of the nanobridge can be characterized by larger plastic strain. A large plastic deformation is an indication that the structure is highly stable. The BCH nanobridge structure also shows enhanced mechanical properties such as higher fracture toughness and higher failure strain. The effect of temperature, strain rate and size of the nanowire on the formation of BCH structure is also explained in details. We also show that the initial orientation of the nanowires play an important role on the formation of BCH crystalline structure. Results indicate that proper tailoring of temperature and strain rate during processing or in the device can lead to very long BCH nanobridge structure of Cu with enhanced mechanical properties, which may find potential application for nano-scale electronic circuits.

Bounds on Defect Level and Fault Coverage in Linear Analog Circuit Testing

Transfer function coefficients (TFC) are widely used to test linear analog circuits for parametric and catastrophic faults. This paper presents closed form expressions for an upper bound on the defect level (DL) and a lower bound on fault coverage (FC) achievable in TFC based test method. The computed bounds have been tested and validated on several benchmark circuits. Further, application of these bounds to scalable RC ladder networks reveal a number of interesting characteristics. The approach adopted here is general and can be extended to find bounds of DL and FC of other parametric test methods for linear and non-linear circuits.

Generation of Minimum Leakage Input Vectors with Constrained NBTI Degradation

Technology scaling has caused Negative Bias Temperature Instability (NBTI) to emerge as a major circuit reliability concern. Simultaneously leakage power is becoming a greater fraction of the total power dissipated by logic circuits. As both NBTI and leakage power are highly dependent on vectors applied at the circuit’s inputs, they can be minimized by applying carefully chosen input vectors during periods when the circuit is in standby or idle mode. Unfortunately input vectors that minimize leakage power are not the ones that minimize NBTI degradation, so there is a need for a methodology to generate input vectors that minimize both of these variables.This paper proposes such a systematic methodology for the generation of input vectors which minimize leakage power under the constraint that NBTI degradation does not exceed a specified limit. These input vectors can be applied at the primary inputs of a circuit when it is in standby/idle mode and are such that the gates dissipate only a small amount of leakage power and also allow a large majority of the transistors on critical paths to be in the “recovery” phase of NBTI degradation. The advantage of this methodology is that allowing circuit designers to constrain NBTI degradation to below a specified limit enables tighter guardbanding, increasing performance. Our methodology guarantees that the generated input vector dissipates the least leakage power among all the input vectors that satisfy the degradation constraint. We formulate the problem as a zero-one integer linear program and show that this formulation produces input vectors whose leakage power is within 1% of a minimum leakage vector selected by a search algorithm and simultaneously reduces NBTI by about 5.75% of maximum circuit delay as compared to the worst case NBTI degradation. Our paper also proposes two new algorithms for the identification of circuit paths that are affected the most by NBTI degradation. The number of such paths identified by our algorithms are an order of magnitude fewer than previously proposed heuristics.

Necessity for quatum simulation for future technology nodes

In this paper we present and compare the results obtained from semi-classical and quantum mechanical simulation for a double gate MOSFET structure to analyze the electrostatics and carrier dynamics of this device. The geometries like gate length, body thickness of this device have been chosen according to the ITRS specification for the different technology nodes. We have shown the extent of deviation between the semi- classical and quantum mechanical results and hence the need of quantum simulations for the promising nanoscale devices in the future technology nodes predicted in ITRS.