Two new families of low-correlation interleaved QAM sequence

Two families of low correlation QAM sequences are presented here. In a CDMA setting, these sequences have the ability to transport a large amount of data as well as enable variable-rate signaling on the reverse link. The first family Á2SQ - B2− is constructed by interleaving 2 selected QAM sequences. This family is defined over M 2-QAM, where M = 2 m , m ≥ 2. Over 16-QAM, the normalized maximum correlation [`(q)]maxmax is bounded above by <~1.17 ÖNUnknown control sequence '\lesssim' , where N is the period of the sequences in the family. This upper bound on [`(q)]maxmax is the lowest among all known sequence families over 16-QAM.The second family Á4SQ4 is constructed by interleaving 4 selected QAM sequences. This family is defined over M 2-QAM, where M = 2 m , m ≥ 3, i.e., 64-QAM and beyond. The [`(q)]maxmax for sequences in this family over 64-QAM is upper bounded by <~1.60 ÖNUnknown control sequence '\lesssim' . For large M, [`(q)]max <~1.64 ÖNUnknown control sequence '\lesssim' . These upper bounds on [`(q)]maxmax are the lowest among all known sequence families over M 2-QAM, M = 2 m , m ≥ 3.

A Multilevel inverter structure with cascaded two level and three level inverters for IM drive with CMV elimination and DC link capacitor voltage balancing

Common mode voltage (CMV) variations in PWM inverter-fed drives generate unwanted shaft and bearing current resulting in early motor failure. Multilevel inverters reduce this problem to some extent, with higher number of levels. But the complexity of the power circuit increases with an increase in the number of inverter voltage levels. In this paper a five-level inverter structure is proposed for open-end winding induction motor (IM) drives, by cascading only two conventional two-level and three-level inverters, with the elimination of the common mode voltage over the entire modulation range. The DC link power supply requirement is also optimized by means of DC link capacitor voltage balancing, with PWM control, using only inverter switching state redundancies. The proposed power circuit gives a simple power bus structure.

Reduced Rate Ultra Low Delay Audio Coder using Multistage Vector Quantization

Communication applications are usually delay restricted, especially for the instance of musicians playing over the Internet. This requires a one-way delay of maximum 25 msec and also a high audio quality is desired at feasible bit rates. The ultra low delay (ULD) audio coding structure is well suited to this application and we investigate further the application of multistage vector quantization (MSVQ) to reach a bit rate range below 64 Kb/s, in a scalable manner. Results at 32 Kb/s and 64 Kb/s show that the trained codebook MSVQ performs best, better than KLT normalization followed by a simulated Gaussian MSVQ or simulated Gaussian MSVQ alone. The results also show that there is only a weak dependence on the training data, and that we indeed converge to the perceptual quality of our previous ULD coder at 64 Kb/s.

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations

Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters. Hence these models are hard to use directly to make high level microarchitectural trade-offs in the initial exploration phase of a design. In this paper, we propose INTACTE, a tool that can be used by architects toget reasonably accurate interconnect area, delay, and power estimates based on a few architecture level parameters for the interconnect such as length, width (in number of bits), frequency, and latency for a specified technology and voltage. The tool uses well known models of interconnect delay and energy taking into account the wire pitch, repeater size, and spacing for a range of voltages and technologies.It then solves an optimization problem of finding the lowest energy interconnect design in terms of the low level circuit parameters, which meets the architectural constraintsgiven as inputs. In addition, the tool also provides the area, energy, and delay for a range of supply voltages and degrees of pipelining, which can be used for micro-architectural exploration of a chip. The delay and energy models used by the tool have been validated against low level circuit simulations. We discuss several potential applications of the tool and present an example of optimizing interconnect design in the context of clustered VLIW architectures. Copyright 2007 ACM.

Compiler-Directed Dynamic Voltage Scaling using Program Phases

Energy consumption has become a major constraint in providing increased functionality for devices with small form factors. Dynamic voltage and frequency scaling has been identified as an effective approach for reducing the energy consumption of embedded systems. Earlier works on dynamic voltage scaling focused mainly on performing voltage scaling when the CPU is waiting for memory subsystem or concentrated chiefly on loop nests and/or subroutine calls having sufficient number of dynamic instructions. This paper concentrates on coarser program regions and for the first time uses program phase behavior for performing dynamic voltage scaling. Program phases are annotated at compile time with mode switch instructions. Further, we relate the Dynamic Voltage Scaling Problem to the Multiple Choice Knapsack Problem, and use well known heuristics to solve it efficiently. Also, we develop a simple integer linear program formulation for this problem. Experimental evaluation on a set of media applications reveal that our heuristic method obtains a 38% reduction in energy consumption on an average, with a performance degradation of 1% and upto 45% reduction in energy with a performance degradation of 5%. Further, the energy consumed by the heuristic solution is within 1% of the optimal solution obtained from the ILP approach.

Hydrothermal synthesis of CdTe QDs: Their luminescence quenching in the presence of bio-molecules and observation of bistable memory effect in CdTe QD/PEDOT:PSS heterostructure

We report one-pot hydrothermal synthesis of nearly mono-disperse 3-mercaptopropionic acid capped water-soluble cadmium telluride (CdTe) quantum dots (QDs) using an air stable Te source. The optical and electrical characteristics were also studied here. It was shown that the hydrothermal synthesis could be tuned to synthesize nano structures of uniform size close to nanometers. The emissions of the CdTe QDs thus synthesized were in the range of 500-700 nm by varying the duration of synthesis. The full width at half maximum (FWHM) of the emission peaks is relatively narrow (40-90 nm), which indicates a nearly uniform distribution of QD size. The structural and optical properties of the QDs were characterized by transmission electron microscopy (TEM), photoluminescence (PL) and Ultraviolet-visible (UV-Vis) spectroscopy. The photoluminescence quenching of CdTe QDs in the presence of L-cysteine and DNA confirms its biocompatibility and its utility for biosensing applications. The room temperature current-voltage characteristics of QD film on ITO coated glass substrate show an electrically induced switching between states with high and low conductivities. The phenomenon is explained on the basis of charge confinement in quantum dots. (C) 2011 Elsevier B.V. All rights reserved.

Voltage and Temperature-Aware SSTA Using Neural Network Delay Model

With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4x less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.

Applications of solid electrolytes in galvanic sensors

The concepts and theoretical origins of conduction domains for solid electrolytes and electrode polarization are outlined briefly. The point electrode made of the ' solid electrolyte material is useful for deflecting the semipermeability flux away from the electrode. The emf of galvanic sensors consisting of two solid electrolytes in intimate contact with each other and in which transport occurs by a common ion is reviewed. The voltage of such cells depends on the chemical potential of the active species at the interface between the two electrolytes, which can be evaluated from the transport properties of electrolytes using a numerical procedure. The factors governing the speed of response of solid electrolyte gas sensors are analyzed. A rigorous expression for the emf of non-isothermal galvanic sensors and the criterion for the design of temperature compensated reference electrodes for nonisothermal galvanic sensors are outlined. Non-isothermal sensors are useful for the continuous monitoring of concentrations or chemical potentials in reactive systems at high temperatures. The principles of operation of galvanic sensors for oxygen, sulphur, oxides of sulphur (SOx,x=2,3), carbon, oxides uf carbon (COx,x= 1,2), oxides of nitrogen (NOx,x= 1,2) and silicon are discussed. The use of auxiliary electrodes in galvanic sensors to expand the detection capability of known solid electrolytes to a large number of species is explained with reference to sensors for sulphur and oxides of sulphur (SOx,x=2,3).Finally the cause of the common errors in galvanic measurements and test for the correct functioning of galvanic sensors is given.

Structural and electrical properties of low pressure metalorganic chemical vapor deposition grown Eu2O3 films on Si(100)

Structural and electrical properties of Eu2O3 films grown on Si(100) in 500–600 °C temperature range by low pressure metalorganic chemical vapor deposition are reported. As-grown films also possess the impurity Eu1−xO phase, which has been removed upon annealing in O2 ambient. Film’s morphology comprises uniform spherical mounds (40–60 nm). Electrical properties of the films, as examined by capacitance-voltage measurements, exhibit fixed oxide charges in the range of −1.5×1011 to −6.0×1010 cm−2 and dielectric constant in the range of 8–23. Annealing has resulted in drastic improvement of their electrical properties. Effect of oxygen nonstoichiometry on the film’s property is briefly discussed.

Elerctron Transport Coefficients in N2 in Crossed Fields at Low E/p

The numerical solutions of Boltzmann transpott equation for the energy distribution of electrons moving in crossed fields in nitrogen have been obtained for 100 ÿ E/p ÿ 1000 V M-1 Torr-1 and for 0ÿ B/p ÿ 0.02 Tesla Torr-1 using the concept of energy dependent effective field intensity. From the derived distribution functions the electron mean energy, the tranaverse and perpendicular drift velocities and the averaged effective field intensity (Eavef) which signifies the average field intensity experienced by electron swarms in E àB field have been derived. The maximum difference between the electron mean energy for a given E ÃÂB field and that corresponding to Eavef/p (p is the gas pressure) is found to be within ñ3.5%.

Fast Direct Torque Control of an Open-End Induction Motor Drive Using 12-Sided Polygonal Voltage Space Vectors

A torque control scheme, based on a direct torque control (DTC) algorithm using a 12-sided polygonal voltage space vector, is proposed for a variable speed control of an open-end induction motor drive. The conventional DTC scheme uses a stator flux vector for the sector identification and then the switching vector to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady-state model of IM and the synchronous frequency of operation is derived from the computed stator flux using a low-pass filter technique. The proposed DTC scheme utilizes the exact positions of the fundamental stator voltage vector and stator flux vector to select the optimal switching vector for fast control of torque with small variation of stator flux within the hysteresis band. The present DTC scheme allows full load torque control with fast transient response to very low speeds of operation, with reduced switching frequency variation. Extensive experimental results are presented to show the fast torque control for speed of operation from zero to rated.

The effect of particle size on performance of cathode materials of Li-ion batteries

Beginning with the ‘frog-leg experiment’ by Galvani (1786), followed by the demonstrations of Volta pile by Volta (1792) and lead-acid accumulator by Plante´ (1859), several battery chemistries have been developed and realized commercially. The development of lithium-ion rechargeable battery in the early 1990s is a breakthrough in the science and technology of batteries. Owing to its high energy density and high operating voltage, the Li-ion battery has become the battery of choice for various portable applications such as note-book computers, cellular telephones, camcorders, etc. Huge efforts are underway in succeeding the development of large size batteries for electric vehicle applications. The origin of lithium-ion battery lies in the discovery that Li+-ions can reversibly be intercalated into/de-intercalated from the Van der Walls gap between graphene sheets of carbon materials at a potential close to the Li/Li+ electrode. By employing carbon as the negative electrode material in rechargeable lithium-ion batteries, the problems associated with metallic lithium in rechargeable lithium batteries have been mitigated. Complimentary investigations on intercalation compounds based on transition metals have resulted in establishing LiCoO2 as the promising cathode material. By employing carbon and LiCoO2, respectively, as the negative and positive electrodes in a non-aqueous lithium-salt electrolyte,a Li-ion cell with a voltage value of about 3.5 V has resulted.Subsequent to commercialization of Li-ion batteries, a number of research activities concerning various aspects of the battery components began in several laboratories across the globe. Regarding the positive electrode materials, research priorities have been to develop different kinds of active materials concerning various aspects such as safety, high capacity, low cost, high stability with long cycle-life, environmental compatibility,understanding relationships between crystallographic and electrochemical properties. The present review discusses the published literature on different positive electrode materials of Li-ion batteries, with a focus on the effect of particle size on electrochemical performance.

Low-inductance axial flux BLDC motor drive for more electric aircraft

As aircraft technology is moving towards more electric architecture, use of electric motors in aircraft is increasing. Axial flux BLDC motors (brushless DC motors) are becoming popular in aero application because of their ability to meet the demand of light weight, high power density, high efficiency and high reliability. Axial flux BLDC motors, in general, and ironless axial flux BLDC motors, in particular, come with very low inductance Owing to this, they need special care to limit the magnitude of ripple current in motor winding. In most of the new more electric aircraft applications, BLDC motor needs to be driven from 300 or 600 Vdc bus. In such cases, particularly for operation from 600 Vdc bus, insulated-gate bipolar transistor (IGBT)-based inverters are used for BLDC motor drive. IGBT-based inverters have limitation on increasing the switching frequency, and hence they are not very suitable for driving BLDC motors with low winding inductance. In this study, a three-level neutral point clamped (NPC) inverter is proposed to drive axial flux BLDC motors. Operation of a BLDC motor driven from three-level NPC inverter is explained and experimental results are presented.

Beat frequency oscillations in the output voltage of high voltage DC power supplies under pulsed loading

High voltage power supplies for radar applications are investigated, which are subjected to pulsed load (125 kHz and 10% duty cycle) with stringent specifications (<0.01% regulation, efficiency>85%, droop<0.5 V/micro-sec.). As good regulation and stable operation requires the converter to be switched at much higher frequency than the pulse load frequency, transformer poses serious problems of insulation failure and higher losses. Few converter topologies are proposed to tackle these problems. A study is made regarding the beat frequency oscillations that may exist with pulsed loading. It is illustrated with respect to the proposed converter topologies. Methods are proposed to eliminate or minimize these oscillations.

Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications. Specifically, this paper attempts to answer the following questions: (1) How much of instruction reuse is inherent in network processing applications?, (2) Can reuse be improved by reducing interference in the reuse buffer?, (3) What characteristics of network applications can be exploited to improve reuse?, and (4) What is the effect of reuse on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. "flows" with a low level microarchitectural feature of programs i.e. repetition of instructions and data along with an architecture that exploits temporal locality in incoming packet data to improve reuse. We find that for the benchmarks considered, 1% to 50% of instructions are reused while the speedup achieved varies between 1% and 24%. As a side effect, instruction reuse reduces memory traffic and can therefore be considered as a scheme for low power.