229 resultados para Aeg-Aug


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Two models for large eddy simulation of turbulent reacting flow in homogeneous turbulence were studied. The sub-grid stress arising out of non-linearities of the Navier-Stokes equations were modeled using an explicit filtering approach. A filtered mass density function (FMDF) approach was used for closure of the sub-grid scalar fluctuations. A posteriori calculations, when compared with the results from the direct numerical simulation, indicate that the explicit filtering is adequate in representing the effect of sub-grid stress on the filtered velocity field in the absence of reaction. Discrepancies arise when reactions occur, but the FMDF approach suffices to account for sub-grid scale fluctuations of the reacting scalars, accurately.

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The main idea proposed in this paper is that in a vertically aligned array of short carbon nanotubes (CNTs) grown on a metal substrate, we consider a frequency dependent electric field, so that the mode-specific propagation of phonons, in correspondence with the strained band structure and the dispersion curves, take place. We perform theoretical calculations to validate this idea with a view of optimizing the field emission behavior of the CNT array. This is the first approach of its kind, and is in contrast to the the conventional approach where a DC bias voltage is applied in order to observe field emission. A first set of experimental results presented in this paper gives a clear indication that phonon-assisted control of field emission current in CNT based thin film diode is possible.

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We propose the design and implementation of hardware architecture for spatial prediction based image compression scheme, which consists of prediction phase and quantization phase. In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates an error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. The software model is tested for its performance in terms of entropy, standard deviation. The memory and silicon area constraints play a vital role in the realization of the hardware for hand-held devices. The hardware architecture is constructed for the proposed scheme, which involves the aspects of parallelism in instructions and data. The processor consists of pipelined functional units to obtain the maximum throughput and higher speed of operation. The hardware model is analyzed for performance in terms throughput, speed and power. The results of hardware model indicate that the proposed architecture is suitable for power constrained implementations with higher data rate