Maximum compatible classes from compatibility matrices

A fast algorithm for the computation of maximum compatible classes (mcc) among the internal states of an incompletely specified sequential machine is presented in this paper. All the maximum compatible classes are determined by processing compatibility matrices of progressingly diminishing order, whose total number does not exceed (p + m), where p is the largest cardinality among these classes, and m is the number of such classes. Consequently the algorithm is specially suitable for the state minimization of very large sequential machines as encountered in vlsi circuits and systems.

A unified model for auxiliary switch commutated DC-DC converters

A novel ZVS auxiliary switch commutated variation for all DGDC converter topologies has been proposed in 2006. With proper designation of the circuit variables (throw current I and the pole voltage V), all these converters are seen to be governed by an identical set of equations. With idealized switches, the steady-state performance is obtainable in an analytical form. The conversion ratio of the converter topologies is obtained. A generalized equivalent circuit emerges for all these converters from the steady-state conversion ratio. It also provides a dynamic model as well. With these generalized steady-state equivalent circuits, small signal analysis of these converters may be carried out readily. It enables one to use the familiar state space averaged results of the standard PWM DGDC converters for the resonant counterparts. Th dc and ac models reveals that dc and low frequency behaviour of the proposed family of converters is similiar to that of its PWM parent

Parallel circuit partitioning on a reduced array architecture

The physical design of a VLSI circuit involves circuit partitioning as a subtask. Typically, it is necessary to partition a large electrical circuit into several smaller circuits such that the total cross-wiring is minimized. This problem is a variant of the more general graph partitioning problem, and it is known that there does not exist a polynomial time algorithm to obtain an optimal partition. The heuristic procedure proposed by Kernighan and Lin1,2 requires O(n2 log2n) time to obtain a near-optimal two-way partition of a circuit with n modules. In the VLSI context, due to the large problem size involved, this computational requirement is unacceptably high. This paper is concerned with the hardware acceleration of the Kernighan-Lin procedure on an SIMD architecture. The proposed parallel partitioning algorithm requires O(n) processors, and has a time complexity of O(n log2n). In the proposed scheme, the reduced array architecture is employed with due considerations towards cost effectiveness and VLSI realizability of the architecture.The authors are not aware of any earlier attempts to parallelize a circuit partitioning algorithm in general or the Kernighan-Lin algorithm in particular. The use of the reduced array architecture is novel and opens up the possibilities of using this computing structure for several other applications in electronic design automation.

An Inexpensive Digital Network Analyzer

Frequency response analysis is critical in understanding the steady and transient state behavior of any electrical network. Network analyzeror frequency response analyzer is used to determine the frequency response of an electrical network. This paper deals with the design of an inexpensive digitally controlled Network Analyzer. The frequency range of the network analyzer is from 10Hz to 50kHz (suitable range for system studies on most power electronics apparatus). It is composed of a microcontroller (as central processing unit) and a personal computer (as analyzer and display). The communication between the microcontroller and personal computer is established through one of the USB ports. The testing and evaluation of the analyzer is done with RC, RLC and multi-resonant circuits. The design steps, basis of analysis, experimental results, limitation in bandwidth and possible techniques for improvement in performances are presented.

Steady-State Stability of Current Mode Active-Clamp ZVS DC-DC Converters

Active-clamp dc-dc converters are pulsewidth-modulated converters having two switches featuring zero-voltage switching at frequencies beyond 100 kHz. Generalized equivalent circuits valid for steady-state and dynamic performance have been proposed for the family of active-clamp converters. The active-clamp converter is analyzed for its dynamic behavior under current control in this paper. The steady-state stability analysis is presented. On account of the lossless damping inherent in the active-clamp converters, it appears that the stability region in the current-controlled active-clamp converters get extended for duty ratios, a little greater than 0.5, unlike in conventional hard-switched converters. The conventional graphical approach fails to assess the stability of current-controlled active-clamp converters due to the coupling between the filter inductor current and resonant inductor current. An analysis that takes into account the presence of the resonant elements is presented to establish the condition for stability. This method correctly predicts the stability of the current-controlled active-clamp converters. A simple expression for the maximum duty cycle for subharmonic free operation is obtained. The results are verified experimentally.

Research note A novel BIMOS Schmitt trigger

A new Schmitt trigger circuit based on the lambda bipolar transistor is presented. This circuit which exhibits a hysteresis in its transfer characteristic seems to use a smaller chip area than many of the circuits proposed so far.

Neural network based approach to standard cell placement

We propose a novel algorithm for placement of standard cells in VLSI circuits based on an analogy of this problem with neural networks. By employing some of the organising principles of these nets, we have attempted to improve the behaviour of the bipartitioning method as proposed by Kernighan and Lin. Our algorithm yields better quality placements compared with the above method, and also makes the final placement independent of the initial partition.

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks

Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process parameters, supply voltage and temperature can be modeled accurately with ANNs. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean and variance. We propose the use of a new activation function that allows us to derive an analytical expression for the mean and a semi-analytical expression for the variance of the ANN-based leakage model. To the best of our knowledge this is the first result in this direction. Our neural network model also includes the voltage and temperature as input parameters, thereby enabling voltage and temperature aware statistical leakage analysis (SLA). All existing SLA frameworks are closely tied to the exponential polynomial leakage model and hence fail to work with sophisticated ANN models. In this paper, we also set up an SLA framework that can efficiently work with these ANN models. Results show that the cumulative distribution function of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values.

On Minimization of Test Application Time for RAS

Conventional Random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design In this paper, we present two cluster based techniques, namely, Serial Input Random Access Scan and Variable Word Length Random Access Scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume

A simple and inexpensive two channel boxcar integrator

A two-channel boxcar integrator with an analog to digital converter was constructed using integrated circuits wherever convenient. The digital output can be instantaneously displayed or displayed after accumulating many samplings in the totaliser. The totaliser mode provides averaging at the digitiser level and hence the integrator has an infinite holding time. When used in the double boxcar mode the instrument overcomes the problem of any base line instability.

A Circuit-Based Proof of Toda′s Theorem

We present a simple proof of Toda′s result (Toda (1989), in "Proceedings, 30th Annual IEEE Symposium on Foundations of Computer Science," pp. 514-519), which states that circled plus P is hard for the Polynomial Hierarchy under randomized reductions. Our approach is circuit-based in the sense that we start with uniform circuit definitions of the Polynomial Hierarchy and apply the Valiant-Vazirani lemma on these circuits (Valiant and Vazirani (1986), Thoeret. Comput. Sci.47, 85-93).

A novel laser direct write technique for fabrication of thin film MICs

A technique for fabrication of thin-film circuits for microwave integrated circuit (MIC) application is presented. This low-cost fabrication technique utilizes laser direct write of copper patterns on alumina substrates. The method obviates the need for photomasks and photolithography. The film deposition mechanism, deposit film analysis, and MIC fabrication sequence are presented. Performance evaluation of MICs fabricated using this technique is also included

A Simple Programmable 2-Pulse Generator for Pulsed NMR NQR Applications

Programmable pulse generator (PPG) circuits using programmable interval timer chips are normally based on a PC or a microprocessor. We describe here a simple low cost programmable two-pulse generator using Intel 8253s in a stand-alone mode, eliminating the need for a PC or a microprocessor, though our design also can be operated via a PC or a microprocessor.

Laser patterning system for integrated optics and storage applications

A computer-controlled laser writing system for optical integrated circuits and data storage is described. The system is characterized by holographic (649F) and high-resolution plates. A minimum linewidth of 2.5 mum is obtained by controlling the system parameters. We show that this system can also be used for data storage applications.

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.