Low-voltage and high-current delay characteristics of a simple triggered vacuum gap

Low-voltage and high-current switching delay characteristics of a simple triggered vacuum gap (TVG) are described using lead zirconate titanate as the dielectric material in the auxiliary gap. This TVG has superior performance at high currents (up to 14 kA was studied) with regard to delay, reliable firing and extended life as compared to the one using either supramica or silicon carbide. The total delay consists of three intervals: to break down the auxiliary gap, to propagate the trigger plasma and to break down the main gap. The data on the influence of the various parameters like the trigger voltage, current, energy and the main circuit energy are given. It has been found that the delay due to the first two intervals is small compared to the third.

Firing delay scheme for 3-Ï thyristor converters

A simple firing delay circuit for 3-φ fully controlled bridge using a phase locked loop is described. The circuit uses very few components and is an improved scheme over the existing methods. The use of this circuit in three-phase thyristor converters and 'circulating current free' mode dual converters is described.

Negative sequence compensation within fundamental positive sequence reference frame for a stiff micro-grid generation in a wind power system using slip ring induction machine

An isolated wind power generation scheme using slip ring induction machine (SRIM) is proposed. The proposed scheme maintains constant load voltage and frequency irrespective of the wind speed or load variation. The power circuit consists of two back-to-back connected inverters with a common dc link, where one inverter is directly connected to the rotor side of SRIM and the other inverter is connected to the stator side of the SRIM through LC filter. Developing a negative sequence compensation method to ensure that, even under the presence of unbalanced load, the generator experiences almost balanced three-phase current and most of the unbalanced current is directed through the stator side converter is the focus here. The SRIM controller varies the speed of the generator with variation in the wind speed to extract maximum power. The difference of the generated power and the load power is either stored in or extracted from a battery bank, which is interfaced to the common dc link through a multiphase bidirectional fly-back dc-dc converter. The SRIM control scheme, maximum power point extraction algorithm and the fly-back converter topology are incorporated from available literature. The proposed scheme is both simulated and experimentally verified.

Integrated CMOS Gas Sensors

We present a low power gas sensor system on CMOS platform consisting of micromachined polysilicon microheater, temperature controller circuit, resistance readout circuit and SnO2 transducer film. The design criteria for different building blocks of the system is elaborated The microheaters are optimized for temperature uniformity as well as static and dynamic response. The electrical equivalent model for the microheater is derived by extracting thermal and mechanical poles through extensive laser doppler vibrometer measurements. The temperature controller and readout circuit are realized on 130nm CMOS technology The temperature controller re-uses the heater as a temperature sensor and controls the duty cycle of the waveform driving the gate of the power MOSFET which supplies heater current. The readout circuit, with subthreshold operation of the MOSFETs, is based oil resistance to time period conversion followed by frequency to digital converter Subthreshold operatin of MOSFETs coupled with sub-ranging technique, achieves ultra low power consumption with more than five orders of magnitude dynamic range RF sputtered SnO2 film is optimized for its microstructure to achive high sensitivity to sense LPG gas.

Inverted slot-mode slow-wave structures for traveling-wave tubes

The dispersion and impedance characteristics of an inverted slot-mode (ISM) slow-wave structure computed by three different techniques, i.e., an analytical model based on a periodic quasi-TEM approach, an equivalent-circuit model, and 3-D electromagnetic simulation are obtained and compared. The comparison was carried out for three different slot-mode structures at S-, C-, and X-bands. The approach was also validated with experimental measurements on a practical X-band ISM traveling-wave tube. The design of ferruleless ISM slow-wave structures, both in circular and rectangular formats, has also been proposed and the predicted dispersion characteristics for these two geometries are compared with 3-D simulation and cold-test measurements. The impedance characteristics for all three designs are also compared.

Modeling and analysis of a tunable piezoelectric structure for transverse shear wave generation

An analytical investigation of the transverse shear wave mode tuning with a resonator mass (packing mass) on a Lead Zirconium Titanate (PZT) crystal bonded together with a host plate and its equivalent electric circuit parameters are presented. The energy transfer into the structure for this type of wave modes are much higher in this new design. The novelty of the approach here is the tuning of a single wave mode in the thickness direction using a resonator mass. First, a one-dimensional constitutive model assuming the strain induced only in the thickness direction is considered. As the input voltage is applied to the PZT crystal in the thickness direction, the transverse normal stress distribution induced into the plate is assumed to have parabolic distribution, which is presumed as a function of the geometries of the PZT crystal, packing mass, substrate and the wave penetration depth of the generated wave. For the PZT crystal, the harmonic wave guide solution is assumed for the mechanical displacement and electric fields, while for the packing mass, the former is solved using the boundary conditions. The electromechanical characteristics in terms of the stress transfer, mechanical impedance, electrical displacement, velocity and electric field are analyzed. The analytical solutions for the aforementioned entities are presented on the basis of varying the thickness of the PZT crystal and the packing mass. The results show that for a 25% increase in the thickness of the PZT crystal, there is ~38% decrease in the first resonant frequency, while for the same change in the thickness of the packing mass, the decrease in the resonant frequency is observed as ~35%. Most importantly the tuning of the generated wave can be accomplished with the packing mass at lower frequencies easily. To the end, an equivalent electric circuit, for tuning the transverse shear wave mode is analyzed.

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Slim P‐E hysteresis loop and anomalous dielectric response in sol-gel derived antiferroelectric PbZrO3 thin films

Sol-gel derived PbZrO3 (PZ) thin films have been deposited on Pt(111)/Ti/SiO2/Si substrate and according to the pseudotetragonal symmetry of PZ, the relatively preferred (110)t oriented phase formation has been noticed. The room temperature P‐E hysteresis loops have been observed to be slim by nature. The slim hysteresis loops are attributed to the [110]t directional antiparallel lattice motion of Pb ions and by the directionality of the applied electric field. Pure PZ formation has been characterized by the dielectric phase transition at 235 °C and antiferroelectric P‐E hysteresis loops at room temperature. Dielectric response has been characterized within a frequency domain of 100 Hz–1 MHz at various temperatures ranging from 40 to 350 °C. Though frequency dispersion of dielectric behaves like a Maxwell–Wagner type of relaxation, ω2 dependency of ac conductivity indicates that there must be G‐C equivalent circuit dominance at high frequency. The presence of trap charges in PZ has been determined by Arrhenius plots of ac conductivity. The temperature dependent n (calculated from the universal power law of ac conductivity) values indicate an anomalous behavior of the trapped charges. This anomaly has been explained by strongly and weakly correlated potential wells of trapped charges and their behavior on thermal activation. The dominance of circuit∕circuits resembling Maxwell–Wagner type has been investigated by logarithmic Nyquist plots at various temperatures and it has been justified that the dielectric dispersion is not from the actual Maxwell–Wagner-type response.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantizationmainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as ``quantization threshold'') that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studiedfor the current-biased negative differential resistance (NDR) circuitand hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

Rendering stiffer walls: a hybrid haptic system using continuous and discrete time feedback

Instability in conventional haptic rendering destroys the perception of rigid objects in virtual environments. Inherent limitations in the conventional haptic loop restrict the maximum stiffness that can be rendered. In this paper we present a method to render virtual walls that are much stiffer than those achieved by conventional techniques. By removing the conventional digital haptic loop and replacing it with a part-continuous and part-discrete time hybrid haptic loop, we were able to render stiffer walls. The control loop is implemented as a combinational logic circuit on an field-programmable gate array. We compared the performance of the conventional haptic loop and our hybrid haptic loop on the same haptic device, and present mathematical analysis to show the limit of stability of our device. Our hybrid method removes the computer-intensive haptic loop from the CPU-this can free a significant amount of resources that can be used for other purposes such as graphical rendering and physics modeling. It is our hope that, in the future, similar designs will lead to a haptics processing unit (HPU).

A simple analog controller for single-phase half-bridge rectifier and its application to transformerless UPS

A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.

A Proportional plus Multiresonant Controller for Three-Phase Four-Wire High-Frequency Link Inverter

A new solution for unbalanced and nonlinear loads in terms of power circuit topology and controller structure is proposed in this paper. A three-phase four-wire high-frequency ac-link inverter is adopted to cater to such loads. Use of high-frequency transformer results in compact and light-weight systems. The fourth wire is taken out from the midpoint of the isolation transformer in order to avoid the necessity of an extra leg. This makes the converter suitable for unbalanced loads and eliminates the requirements of bulky capacitor in half-bridge inverter. The closed-loop control is carried out in stationary reference frame using proportional + multiresonant controller (three separate resonant controller for fundamental, fifth and seventh harmonic components). The limitations on improving steady-state response of harmonic resonance controllers is investigated and mitigated using a lead-lag compensator. The proposed voltage controller is used along with an inner current loop to ensure excellent performance of the power converter. Simulation studies and experimental results with 1 kVA prototype under nonlinear and unbalanced loading conditions validate the proposed scheme.

Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative

In this brief, we present a new circuit technique to generate the sigmoid neuron activation function (NAF) and its derivative (DNAF). The circuit makes use of transistor asymmetry in cross-coupled differential pair to obtain the derivative. The asymmetry is introduced through external control signal, as and when required. This results in the efficient utilization of the hard-ware by realizing NAF and DNAF using the same building blocks. The operation of the circuit is presented in the subthreshold region for ultra low-power applications. The proposed circuit has been experimentally prototyped and characterized as a proof of concept on the 1.5-mum AMI technology.