168 resultados para Circuit of Sacoleiros


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Among various MEMS sensors, a rate gyroscope is one of the most complex sensors from the design point of view. The gyro normally consists of a proof mass suspended by an elaborate assembly of beams that allow the system to vibrate in two transverse modes. The structure is normally analysed and designed using commercial FEM packages such as ANSYS or MEMS specific commercial tools such as Coventor or Intellisuite. In either case, the complexity in analysis rises manyfolds when one considers the etch hole topography and the associated fluid flow calculation for damping. In most cases, the FEM analysis becomes prohibitive and one resorts to equivalent electrical circuit simulations using tools like SABER in Coventor. Here, we present a simplified lumped parameter model of the tuning fork gyro and show how easily it can be implemented using a generic tool like SIMULINK. The results obtained are compared with those obtained from more elaborate and intense simulations in Coventor. The comparison shows that lumped parameter SIMULINK model gives equally good results with fractional effort in modelling and computation. Next, the performance of a symmetric and decoupled vibratory gyroscope structure is also evaluated using this approach and a few modifications are made in this design to enhance the sensitivity of the device.

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Random Access Scan, which addresses individual flip-flops in a design using a memory array like row and column decoder architecture, has recently attracted widespread attention, due to its potential for lower test application time, test data volume and test power dissipation when compared to traditional Serial Scan. This is because typically only a very limited number of random ``care'' bits in a test response need be modified to create the next test vector. Unlike traditional scan, most flip-flops need not be updated. Test application efficiency can be further improved by organizing the access by word instead of by bit. In this paper we present a new decoder structure that takes advantage of basis vectors and linear algebra to further significantly optimize test application in RAS by performing the write operations on multiple bits consecutively. Simulations performed on benchmark circuits show an average of 2-3 times speed up in test write time compared to conventional RAS.

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This paper presents the analysis and study of voltage collapse at any converter bus in A C-DC systems considering the dynamics of DC system. The problem of voltage instability is acute when HVDC links are connected to weak AC systems, the strength determined by short circuit ratio (SCR) at the converter bus. The converter control strategies are important in determining voltage instability. Small signal analysis is used to identify critical modes and evaluate the effect of AC system strength and control parameters. A sample two-terminal DC system is studied and the results compared with those obtained from static analysis. Also, the results obtained from small signal analysis are validated with nonlinear simulation.

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Anatase titania nanotubes (TNTs) have been synthesized from P25 TiO2 powder by alkali hydrothermal method followed by post annealing. The microstructure analysis by X-ray diffraction (XRD), transmission electron microscopy (TEM) and scanning electron microscopy (SEM) revealed the formation of anatase nanotubes with a diameter of 9-10 nm. These NTs are used to make photo anode in dye-sensitized solar cells (DSSCs). Layer by layer deposition with curing of each layer at 350 C is employed to realize films of desired thickness. The performance of these cells is studied using photovoltaic measurements. Electrochemical impedance spectroscopy (EIS) is used to quantitatively analyze the effect of thickness on the performance of these cells. These studies revealed that the thickness of TiO2 has a pronounced impact on the cell performance and the optimum thickness lies in the range of 10-14 mu m. In comparison to dye solar cells made of P25, TNTs based cells exhibit an improved open circuit voltage and fill factor (FF) due to an increased electron lifetime, as revealed by EIS analysis. (C) 2011 Elsevier B.V. All rights reserved.

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Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

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The internal resistance of a stabilized alpha-nickel hydroxide electrode is found to be lower than that of a beta-nickel hydroxide electrode as shown from studies of the open-circuit potential-time transients at all states-of-charge. Nevertheless, the self-discharge rates of the former is higher. Gasometric studies reveal that the charging efficiency of the alpha-nickel hydroxide electrode is higher than that of the beta-nickel hydroxide electrode.

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Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.

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This paper deals with the system oriented analysis, design, modeling, and implementation of active clamp HF link three phase converter. The main advantage of the topology is reduced size, weight, and cost of the isolation transformer. However, violation of basic power conversion rules due to presence of the leakage inductance in the HF transformer causes over voltage stresses across the cycloconverter devices. It makes use of the snubber circuit necessary in such topologies. The conventional RCD snubbers are dissipative in nature and hence inefficient. The efficiency of the system is greatly improved by using regenerative snubber or active clamp circuit. It consists of an active switching device with an anti-parallel diode and one capacitor to absorb the energy stored in the leakage inductance of the isolation transformer and to regenerate the same without affecting circuit performance. The turn on instant and duration of the active device are selected such that it requires simple commutation requirements. The time domain expressions for circuit dynamics, design criteria of the snubber capacitor with two conflicting constrains (over voltage stress across the devices and the resonating current duration), the simulation results based on generalized circuit model and the experimental results based on laboratory prototype are presented.

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This is an exploratory study to illustrate the feasibility of detecting delamination type of damage in polymeric laminates with one layer of magnetostrictive particles. One such beam encircled with excitation and sensing coils is used for this study. The change in stress gradient of the magnetostrictive layer in the vicinity of delamination shows up as a change in induced voltage in the sensing coil, and therefore provides a means to sense the presence of delamination. Recognizing the constitutive behavior of the Terfenol-D material is highly nonlinear, analytical expressions for the constitutive relations are developed by using curve fitting techniques to the experimental data. Analytical expressions that relate the applied excitation field with the stress and magnetic flux densities induced in the magnetostrictive layer are developed. Numerical methods are used to find the relative change in the induced voltage in the sensing coil due to the presence of delamination. A typical example of unidirectional laminate, with embedded delaminations, is used for the simulation purposes. This exploratory study illustrates that the open-circuit voltage induced in the sensing coil changes significantly (as large of 68 millivolts) with the occurrence of delamination. This feature can be exploited for device off-line inspection techniques and/or linking monitoring procedures for practical applications.

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Capacitive-resistive transients in extended media are discussed in tenns of electric field quantities. Obviously, in rhese problems, the contribution of the magnetlc field to the electric field is deemed negligible. For a simple lllusfratlve example, the field solution is compared with the circuit-theoretical resuit for the voltage and current. An algorithm for solving such transients in space and time doman with the help of a Laplace solver is presented. Any other Laplace solver can also be used far this purpose. Its applicability is demonstrated with three examples, one of which is chosen to have a circuit-theoretical solution.

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In situ annealed thin films of ferroelectric Ba(Zr0.1Ti0.9)O-3 were deposited on platinum substrates by pulsed laser ablation technique. The as grown films were polycrystalline in nature without the evidence of any secondary phases. The polarization hysteresis loop confirmed the ferroelectricity, which was also cross-checked with the capacitance-voltage characteristics. The remnant polarization was about 5.9 muC cm(-2) at room temperature and the coercive field was 45 kV. There was a slight asymmetry in the hysteresis for different polarities, which was thought to be due to the work function differences of different electrodes. The dielectric constant was about 452 and was found to exhibit low frequency dispersion that increased with frequency, This was related to the space-charge polarization. The complex impedance was plotted and this exhibited a semicircular trace, and indicated an equivalent parallel R - C circuit within the sample. This was attributed to the grain response. The DC leakage current-voltage plot was consistent with the space-charge limited conduction theory, but showed some deviation, which was explained by assuming a Poole-Frenkel type conduction to be superimposed on to the usual space-charge controlled current. (C) 2002 Elsevier Science B.V. All rights reserved.

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In this paper, we investigate the effect of vacuum sealing the backside cavity of a Capacitive Micromachined Ultrasonic Transducer (CMUT). The presence or absence of air inside the cavity has a marked effect upon the system parameters, such as the natural frequency, damping, and the pull-in voltage. The presence of vacuum inside the cavity of the device causes a reduction in the effective gap height which leads to a reduction in the pull-in voltage. We carry out ANSYS simulations to quantify this reduction. The presence of vacuum inside the cavity of the device causes stress stiffening of the membrane, which changes the natural frequency of the device. A prestressed modal analysis is carried out to determine the change in natural frequency due to stress stiffening. The equivalent circuit method is used to evaluate the performance of the device in the receiver mode. The lumped parameters of the device are obtained and an equivalent circuit model of the device is constructed to determine the open circuit receiving sensitivity of the device. The effect of air in the cavity is included by incorporating an equivalent compliance and an equivalent resistance in the equivalent circuit.

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A (k-, K) circuit is one which can be decomposed into nonintersecting blocks of gates where each block has no more than K external inputs, such that the graph formed by letting each block be a node and inserting edges between blocks if they share a signal line, is a partial k-tree. (k, K) circuits are special in that they have been shown to be testable in time polynomial in the number of gates in the circuit, and are useful if the constants k and K are small. We demonstrate a procedure to synthesise (k, K) circuits from a special class of Boolean expressions.

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Analytical studies are carried out to minimize acquisition time in phase-lock loop (PLL) applications using aiding functions. A second order aided PLL is realized with the help of the quasi-stationary approach to verify the acquisition behavior in the absence of noise. Time acquisition is measured both from the study of the LPF output transient and by employing a lock detecting and indicating circuit to crosscheck experimental and analytical results. A closed form solution is obtained for the evaluation of the time acquisition using different aiding functions. The aiding signal is simple and economical and can be used with state of the art hardware.

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Load commutated inverter (LCI)-fed wound field synchronous motor drives are used for medium-voltage high-power drive applications. This drive suffers from drawbacks such as complex starting procedure, sixth harmonic torque pulsations, quasi square wave motor current, notches in the terminal voltages, etc. In this paper, a hybrid converter circuit, consisting of an LCI and a voltage source inverter (VSI), is proposed, which can be a universal high-power converter solution for wound field synchronous motor drives. The proposed circuit, with the addition of a current-controlled VSI, overcomes nearly all of the shortcomings present in the conventional LCI-based system besides providing many additional advantages. In the proposed drive, the motor voltage and current are always sinusoidal even with the LCI switching at the fundamental frequency. The performance of the drive is demonstrated with detailed experimental waveforms from a 15.8-hp salient pole wound field synchronous machine. Finally, a brief description of the control scheme used for the proposed circuit is given.