Underlap Optimization in HFinFET in Presence of Interface Traps

In this work, using 3-D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the ON-OFF ratio as well as the subthreshold characteristics in an ultrashort channel n-type device without significantON performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be promising when compared against ITRS 2009 performance projections, as well as published state of the art planar and nonplanar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.

Influence of Gate Corrugations on the Performance of Thin-Film Transistors

This letter investigates the influence of a corrugated gate on the transfer characteristics of thin-film transistors. Corrugations that run parallel to the length of the channel from source to drain are patterned on the gate. The author finds that these corrugations result in higher currents as compared to conventional planar-gate transistors.

Effect of gate-drain/source overlap on the noise in 90 nm N-channel metal oxide semiconductor field effect transistors

In this paper, we have studied the effect of gate-drain/source overlap (LOV) on the drain channel noise and induced gate current noise (SIg) in 90 nm N-channel metal oxide semiconductor field effect transistors using process and device simulations. As the change in overlap affects the gate tunneling leakage current, its effect on shot noise component of SIg has been taken into consideration. It has been shown that “control over LOV” allows us to get better noise performance from the device, i.e., it allows us to reduce noise figure, for a given leakage current constraint. LOV in the range of 0–10 nm is recommended for the 90 nm gate length transistors, in order to get the best performance in radio frequency applications.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Acenaphtho[1,2-b]quinoxaline based low band gap copolymers for organic thin film transistor applications

We report the synthesis of a novel class of low band gap copolymers based on anacenaphtho[1,2-b]quinoxaline core and oligothiophene derivatives acting as the acceptor and the donor moieties, respectively. The optical properties of the copolymers were characterized by ultraviolet-visible spectroscopy while the electrochemical properties were determined by cyclic voltammetry. The band gap of these polymers was found to be in the range 1.8-2.0 eV as calculated from the optical absorption band edge. X-ray diffraction measurements show weak pi-pi stacking interactions between the polymer chains. The hole mobility of the copolymers was evaluated using field-effect transistor measurements yielding values in the range 10(-5)-10(-3) cm(2)/Vs.

Symmetry-dependent phonon renormalization in monolayer MoS2 transistor

A strong electron-phonon interaction which limits the electronic mobility of semiconductors can also have significant effects on phonon frequencies. The latter is the key to the use of Raman spectroscopy for nondestructive characterization of doping in graphene-based devices. Using in situ Raman scattering from a single-layer MoS2 electrochemically top-gated field-effect transistor (FET), we show softening and broadening of the A(1g) phonon with electron doping, whereas the other Raman-active E-2g(1) mode remains essentially inert. Confirming these results with first-principles density functional theory based calculations, we use group theoretical arguments to explain why the A(1g) mode specifically exhibits a strong sensitivity to electron doping. Our work opens up the use of Raman spectroscopy in probing the level of doping in single-layer MoS2-based FETs, which have a high on-off ratio and are of technological significance.

A Simple Charge Model for Symmetric Double-Gate MOSFETs Adapted to Gate-Oxide-Thickness Asymmetry

Surface-potential-based compact charge models for symmetric double-gate metal-oxide-semiconductor field-effect transistors (SDG-MOSFETs) are based on the fundamental assumption of having equal oxide thicknesses for both gates. However, for practical devices, there will always be some amount of asymmetry between the gate oxide thicknesses due to process variations and uncertainties, which can affect device performance significantly. In this paper, we propose a simple surface-potential-based charge model, which is applicable for tied double-gate MOSFETs having same gate work function but could have any difference in gate oxide thickness. The proposed model utilizes the unique so-far-unexplored quasi-linear relationship between the surface potentials along the channel. In this model, the terminal charges could be computed by basic arithmetic operations from the surface potentials and applied biases, and thus, it could be implemented in any circuit simulator very easily and extendable to short-channel devices. We also propose a simple physics-based perturbation technique by which the surface potentials of an asymmetric device could be obtained just by solving the input voltage equation of SDG devices for small asymmetry cases. The proposed model, which shows excellent agreement with numerical and TCAD simulations, is implemented in a professional circuit simulator through the Verilog-A interface and demonstrated for a 101-stage ring oscillator simulation. It is also shown that the proposed model preserves the source/drain symmetry, which is essential for RF circuit design.

Improvements in Efficiency of Surface Potential Computation for Independent DG MOSFET

A robust numerical solution of the input voltage equations (IVEs) for the independent-double-gate metal-oxide-semiconductor field-effect transistor requires root bracketing methods (RBMs) instead of the commonly used Newton-Raphson (NR) technique due to the presence of nonremovable discontinuity and singularity. In this brief, we do an exhaustive study of the different RBMs available in the literature and propose a single derivative-free RBM that could be applied to both trigonometric and hyperbolic IVEs and offers faster convergence than the earlier proposed hybrid NR-Ridders algorithm. We also propose some adjustments to the solution space for the trigonometric IVE that leads to a further reduction of the computation time. The improvement of computational efficiency is demonstrated to be about 60% for trigonometric IVE and about 15% for hyperbolic IVE, by implementing the proposed algorithm in a commercial circuit simulator through the Verilog-A interface and simulating a variety of circuit blocks such as ring oscillator, ripple adder, and twisted ring counter.

Inclusion of body doping in compact models for fully-depleted common double gate MOSFET adapted to gate-oxide thickness asymmetry

Since it is difficult to find the analytical solution of the governing Poisson equation for double gate MOSFETs with the body doping term included, the majority of the compact models are developed for undoped-body devices for which the analytical solution is available. Proposed is a simple technique to included a body doping term in such surface potential based common double gate MOSFET models also by taking into account any differences between the gate oxide thickness. The proposed technique is validated against TCAD simulation and found to be accurate as long as the channel is fully depleted.

Performance and variability trade-off with gate-to-source/drain overlap length

The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Substrate temperature influenced physical properties of silicon MOS devices with TiO2 gate dielectric

DC reactive magnetron sputtering technique was employed for deposition of titanium dioxide (TiO2) films. The films were formed on Corning glass and p-Si (100) substrates by sputtering of titanium target in an oxygen partial pressure of 6x10-2 Pa and at different substrate temperatures in the range 303 673 K. The films formed at 303 K were X-ray amorphous whereas those deposited at substrate temperatures?=?473 K were transformed into polycrystalline nature with anatase phase of TiO2. Fourier transform infrared spectroscopic studies confirmed the presence of characteristic bonding configuration of TiO2. The surface morphology of the films was significantly influenced by the substrate temperature. MOS capacitor with Al/TiO2/p-Si sandwich structure was fabricated and performed currentvoltage and capacitancevoltage characteristics. At an applied gate voltage of 1.5 V, the leakage current density of the device decreased from 1.8?x?10-6 to 5.4?x?10-8 A/cm2 with the increase of substrate temperature from 303 to 673 K. The electrical conduction in the MOS structure was more predominant with Schottky emission and Fowler-Nordheim conduction. The dielectric constant (at 1 MHz) of the films increased from 6 to 20 with increase of substrate temperature. The optical band gap of the films increased from 3.50 to 3.56 eV and refractive index from 2.20 to 2.37 with the increase of substrate temperature from 303 to 673 K. Copyright (c) 2012 John Wiley & Sons, Ltd.

High field carrier transport in graphene: Insights from fast current transient

In this work, we observe gate tunable negative differential conductance (NDC) and current saturation in single layer and bilayer graphene transistor at high source-drain field, which arise due to the interplay among (1) self-heating, (2) hot carrier injection, and (3) drain induced minority carrier injection. The magnitude of the NDC is found to be reduced for a bilayer, in agreement with its weaker carrier-optical phonon coupling and less efficient hot carrier injection. The contributions of different mechanisms to the observed results are decoupled through fast transient measurements with nanosecond resolution. The findings provide insights into high field transport in graphene. (C) 2012 American Institute of Physics. http://dx.doi.org/10.1063/1.4754103]

A low-noise low-power noise-adaptive neural amplifier in 0.13um CMOS technology

Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. The advent of multichannel microelectrode arrays has driven the need for electronics to record neural signals from many neurons. The dynamic range of the system is limited by background system noise which varies over time. We propose a neural amplifier in UMC 130 nm, 2P8M CMOS technology. It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface. The bandwidth of the amplifier can be tuned by the pseudo-resistor for selectively recording low field potentials (LFP) or extra cellular action potentials (EAP). The amplifier achieves a mid-band voltage gain of 37 dB and minimizes the attenuation of the signal from neuron to the gate of the input transistor. It is used in fully differential configuration to reject noise of bias circuitry and to achieve high PSRR.

Performance limits of transition metal dichalcogenide (MX2) nanotube surround gate ballistic field effect transistors

We theoretically analyze the performance of transition metal dichalcogenide (MX2) single wall nanotube (SWNT) surround gate MOSFET, in the 10 nm technology node. We consider semiconducting armchair (n, n) SWNT of MoS2, MoSe2, WS2, and WSe2 for our study. The material properties of the nanotubes are evaluated from the density functional theory, and the ballistic device characteristics are obtained by self-consistently solving the Poisson-Schrodinger equation under the non-equilibrium Green's function formalism. Simulated ON currents are in the range of 61-76 mu A for 4.5 nm diameter MX2 tubes, with peak transconductance similar to 175-218 mu S and ON/OFF ratio similar to 0.6 x 10(5)-0.8 x 10(5). The subthreshold slope is similar to 62.22 mV/decade and a nominal drain induced barrier lowering of similar to 12-15 mV/V is observed for the devices. The tungsten dichalcogenide nanotubes offer superior device output characteristics compared to the molybdenum dichalcogenide nanotubes, with WSe2 showing the best performance. Studying SWNT diameters of 2.5-5 nm, it is found that increase in diameter provides smaller carrier effective mass and 4%-6% higher ON currents. Using mean free path calculation to project the quasi-ballistic currents, 62%-75% reduction from ballistic values in drain current in long channel lengths of 100, 200 nm is observed.