121 resultados para Silicon nanowire


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Silicon oxide films were deposited by reactive evaporation of SiO. Parameters such as oxygen partial pressure and substrate temperature were varied to get variable and graded index films. Films with a refractive index in the range 1.718 to 1.465 at 550 nm have been successfully deposited. Films deposited using ionized oxygen has the refractive index 1.465 at 550 nm and good UV transmittance like bulk fused quartz. Preparation of graded index films was also investigated by changing the oxygen partial pressure during deposition. A two layer antireflection coating at 1064nm has been designed using both homogeneous and inhomogeneous films and studied their characteristics.

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A novel size dependent FCC (face-centered-cubic) -> HCP (hexagonally-closed-pack) phase transformation and stability of an initial FCC zirconium nanowire are studied. FCC zirconium nanowires with cross-sectional dimensions < 20 are found unstable in nature, and they undergo a FCC -> HCP phase transformation, which is driven by tensile surface stress induced high internal compressive stresses. FCC nanowire with cross-sectional dimensions > 20 , in which surface stresses are not enough to drive the phase transformation, show meta-stability. In such a case, an external kinetic energy in the form of thermal heating is required to overcome the energy barrier and achieve FCC -> HCP phase transformation. The FCC-HCP transition pathway is also studied using Nudged Elastic Band (NEB) method, to further confirm the size dependent stability/metastability of Zr nanowires. We also show size dependent critical temperature, which is required for complete phase transformation of a metastable-FCC nanowire.

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InN quantum dots (QDs) were fabricated on silicon nitride/Si (111) substrate by droplet epitaxy. Single-crystalline structure of InN QDs was verified by transmission electron microscopy, and the chemical bonding configurations of InN QDs were examined by x-ray photoelectron spectroscopy. Photoluminescence measurement shows a slight blue shift compared to the bulk InN, arising from size dependent quantum confinement effect. The interdigitated electrode pattern was created and current-voltage (I-V) characteristics of InN QDs were studied in a metal-semiconductor-metal configuration in the temperature range of 80-300K. The I-V characteristics of lateral grown InN QDs were explained by using the trap model. (C) 2011 American Institute of Physics. [doi:10.1063/1.3651762]

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Continuous advances in VLSI technology have made implementation of very complicated systems possible. Modern System-on -Chips (SoCs) have many processors, IP cores and other functional units. As a result, complete verification of whole systems before implementation is becoming infeasible; hence it is likely that these systems may have some errors after manufacturing. This increases the need to find design errors in chips after fabrication. The main challenge for post-silicon debug is the observability of the internal signals. Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall verification effort on large designs, and the problem is growing worse.Traditional post-silicon debug methods concentrate on functional parts of systems and provide mechanisms to increase the observability of internal state of systems. Those methods may not be sufficient as modern SoCs have lots of blocks (processors, IP cores, etc.) which are communicating with one another and communication is another source of design errors. This tutorial will be provide an insight into various observability enhancement techniques, on chip instrumentation techniques and use of high level models to support the debug process targeting both inside blocks and communication among them. It will also cover the use of formal methods to help debug process.

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Electron paramagnetic resonance studies under ambient conditions of boron‐doped porous silicon show anisotropic Zeeman (g) and hyperfine (A) tensors, signaling localization of the charge carriers due to quantum confinement.

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Atomistic simulation of initial < 100 > oriented FCC Cu nanowires shows a novel coupled temperature-pressure dependent reorientation from < 100 > to < 110 > phase. A temperature-pressure-induced solid-solid < 100 > to < 110 > reorientation diagram is generated for Cu nanowire with varying cross-sectional sizes. A critical pressure is reported for Cu nanowires with varying cross-sectional sizes, above which an initial < 100 > oriented nanowire shows temperature independent reorientation into the < 110 > phase. The effect of surface stresses on the < 100 > to < 110 > reorientation is also studied. The results indicate that above a critical cross-sectional size for a given temperature-pressure, < 100 > to < 110 > reorientation is not possible. It is also reported here that for a given applied pressure, an increase in temperature is required for the < 100 > to < 110 > reorientation with increasing cross-sectional size of the nanowire. The temperature-pressure-induced solid-solid < 100 > to < 110 > reorientation diagram reported in the present paper could further be used as guidelines for controlling the reorientations/shape memory in nano-scale applications of FCC metallic nanowires.

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For the first time silicon nanowires have been grown on indium (In) coated Si (100) substrates using e-beam evaporation at a low substrate temperature of 300 degrees C. Standard spectroscopic and microscopic techniques have been employed for the structural, morphological and compositional properties of as grown Si nanowires. The as grown Si nanowires have randomly oriented with an average length of 600 nm for a deposition time of 15 min. As grown Si nanowires have shown indium nanoparticle (capped) on top of it confirming the Vapor Liquid Solid (VLS) growth mechanism. Transmission Electron Microscope (TEM) measurements have revealed pure and single crystalline nature of Si nanowires. The obtained results have indicated good progress towards finding alternative catalyst to gold for the synthesis of Si nanowires. (C) 2011 Elsevier B.V. All rights reserved.

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Abstract | Non-crystalline or glassy semiconductors are of great research interest for the fabrication of large area electronic systems such as displays and image sensors. Good uniformity over large areas, low temperature fabrication and the promise of low cost electronics on large area mechanically flexible and rigid substrates are some attractive features of these technologies. The article focusses on amorphous hydrogenated silicon thin film transistors, and reviews the problems, solutions and applications of these devices.

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In this paper, we propose a physics-based simplified analytical model of the energy band gap and electron effective mass in a relaxed and strained rectangular 100] silicon nanowires (SiNWs). Our proposed formulation is based on the effective mass approximation for the nondegenerate two-band model and 4 x 4 Luttinger Hamiltonian for energy dispersion relation of conduction band electrons and the valence band heavy and light holes, respectively. Using this, we demonstrate the effect of the uniaxial strain applied along 100]-direction and a biaxial strain, which is assumed to be decomposed from a hydrostatic deformation along 001] followed by a uniaxial one along the 100]-direction, respectively, on both the band gap and the transport and subband electron effective masses in SiNW. Our analytical model is in good agreement with the extracted data using the extended-Huckel-method-based numerical simulations over a wide range of device dimensions and applied strain.

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We have demonstrated a simple, scalable and inexpensive method based on microwave plasma for synthesizing 5 to 10 g/h of nanomaterials. Luminescent nano silicon particles were synthesized by homogenous nucleation of silicon vapour produced by the radial injection of silicon tetrachloride vapour and nano titanium nitride was synthesized by using liquid titanium tetrachloride as the precursor. The synthesized nano silicon and titanium nitride powders were characterized by XRD, XPS, TEM, SEM and BET. The characterization techniques indicated that the synthesized powders were indeed crystalline nanomaterials.

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We report on the threshold voltage modeling of ultra-thin (1 nm-5 nm) silicon body double-gate (DG) MOSFETs using self-consistent Poisson-Schrodinger solver (SCHRED). We define the threshold voltage (V th) of symmetric DG MOSFETs as the gate voltage at which the center potential (Φ c) saturates to Φ c (s a t), and analyze the effects of oxide thickness (t ox) and substrate doping (N A) variations on V th. The validity of this definition is demonstrated by comparing the results with the charge transition (from weak to strong inversion) based model using SCHRED simulations. In addition, it is also shown that the proposed V t h definition, electrically corresponds to a condition where the inversion layer capacitance (C i n v) is equal to the oxide capacitance (C o x) across a wide-range of substrate doping densities. A capacitance based analytical model based on the criteria C i n v C o x is proposed to compute Φ c (s a t), while accounting for band-gap widening. This is validated through comparisons with the Poisson-Schrodinger solution. Further, we show that at the threshold voltage condition, the electron distribution (n(x)) along the depth (x) of the silicon film makes a transition from a strong single peak at the center of the silicon film to the onset of a symmetric double-peak away from the center of the silicon film. © 2012 American Institute of Physics.