254 resultados para Power circuit


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The present trend in the industry is towards the use of power transistors in the development of efficient Pulsewidth Modulated (PWM) inverters, because of their operation at high frequency, simplicity of turn-off, and low commutation losses compared to the technology using thyristors. But the protection of power transistors, minimization of switching power loss, and design of base drive circuit are very important for a reliable operation of the system. The requirements, analysis, and a simplified procedure for calculation of the switching-aid network components are presented. The transistor is protected against short circuit using a modified autoregulated and autoprotection drive circuit. The experimental results show that the switching power loss and voltage stress in the device can be reduced by suitable choice of the switching-aid network component values.

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The operation of thyristor-controlled static VAR compensators (SVCs) at various conduction angles can be used advantageously to meet the unablanced reactive power demands in a system. However, such operation introduces harmonic currents into the AC system. This paper presents an algorithm to evaluate an optimum combination of the phase-wise reactive power generations from SVC and balanced reactive power supply from the AC system, based on the defined performance indices, namely, the telephone influence factor (TIF), the total harmonic current factor (IT) and the distortion factor (D). Results of the studies conducted on a typical distribution system are presented and discussed.

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The results are presented of applying multi-time scale analysis using the singular perturbation technique for long time simulation of power system problems. A linear system represented in state-space form can be decoupled into slow and fast subsystems. These subsystems can be simulated with different time steps and then recombined to obtain the system response. Simulation results with a two-time scale analysis of a power system show a large saving in computational costs.

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In this paper, for the first time, the effects of energy quantization on single electron transistor (SET) inverter performance are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantization mainly changes the Coulomb blockade region and drain current of SET devices and thus affects the noise margin, power dissipation, and the propagation delay of SET inverter. A new analytical model for the noise margin of SET inverter is proposed which includes the energy quantization effects. Using the noise margin as a metric, the robustness of SET inverter is studied against the effects of energy quantization. A compact expression is developed for a novel parameter quantization threshold which is introduced for the first time in this paper. Quantization threshold explicitly defines the maximum energy quantization that an SET inverter logic circuit can withstand before its noise margin falls below a specified tolerance level. It is found that SET inverter designed with CT:CG=1/3 (where CT and CG are tunnel junction and gate capacitances, respectively) offers maximum robustness against energy quantization.

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A simple multiple pulsewidth modulated (MPWM) ac chopper using power transistors for 3-¿ power control is discussed. 120° chopping period is used for main transistors so that the circuit can accommodate resistive and lagging or leading power factor loads. Only 1-¿ sensing is used for 3-¿ control. An alternate economical power and control schemes for 3-¿ MPWM ac choppers suitable only for resistive loads is also suggested. The experimental results for 12 choppings per cycle are given.

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A simple linear ramp control circuit, suitable for use with force-commutated thyrister circuits is discussed here. The circuit is based on only two IM 558 dual timer iCs, operating from a single 15 V supply. The reset terminals facilitate inhibition of the output of any stage. The use of this circuit in a thyristor chopper operating at 400 Hz 13 described.

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Contention-based multiple access is a crucial component of many wireless systems. Multiple-packet reception (MPR) schemes that use interference cancellation techniques to receive and decode multiple packets that arrive simultaneously are known to be very efficient. However, the MPR schemes proposed in the literature require complex receivers capable of performing advanced signal processing over significant amounts of soft undecodable information received over multiple contention steps. In this paper, we show that local channel knowledge and elementary received signal strength measurements, which are available to many receivers today, can actively facilitate multipacket reception and even simplify the interference canceling receiver¿s design. We introduce two variants of a simple algorithm called Dual Power Multiple Access (DPMA) that use local channel knowledge to limit the receive power levels to two values that facilitate successive interference cancellation. The resulting receiver structure is markedly simpler, as it needs to process only the immediate received signal without having to store and process signals received previously. Remarkably, using a set of three feedback messages, the first variant, DPMA-Lite, achieves a stable throughput of 0.6865 packets per slot. Using four possible feedback messages, the second variant, Turbo-DPMA, achieves a stable throughput of 0.793 packets per slot, which is better than all contention algorithms known to date.

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In developing countries high rate of growth in demand of electric energy is felt, and so the addition of new generating units becomes necessary. In deregulated power systems private generating stations are encouraged to add new generations. Finding the appropriate location of new generator to be installed can be obtained by running repeated power flows, carrying system studies like analyzing the voltage profile, voltage stability, loss analysis etc. In this paper a new methodology is proposed which will mainly consider the existing network topology into account. A concept of T-index is introduced in this paper, which considers the electrical distances between generator and load nodes.This index is used for ranking significant new generation expansion locations and also indicates the amount of permissible generations that can be installed at these new locations. This concept facilitates for the medium and long term planning of power generation expansions within the available transmission corridors. Studies carried out on a sample 7-bus system, EHV equivalent 24-bus system and IEEE 39 bus system are presented for illustration purpose.

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In this paper a modified Heffron-Phillip's (K-constant) model is derived for the design of power system stabilizers. A knowledge of external system parameters, such as equivalent infinite bus voltage and external impedances or their equivalent estimated values is required for designing a conventional power system stabilizer. In the proposed method, information available at the secondary bus of the step-up transformer is used to set up a modified Heffron-Phillip's (ModHP) model. The PSS design based on this model utilizes signals available within the generating station. The efficacy of the proposed design technique and the performance of the stabilizer has been evaluated over a range of operating and system conditions. The simulation results have shown that the performance of the proposed stabilizer is comparable to that could be obtained by conventional design but without the need for the estimation and computation of external system parameters. The proposed design is thus well suited for practical applications to power system stabilization, including possibly the multi-machine applications where accurate system information is not readily available.

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In this paper, a new approach to enhance the transmission system distance relay co-ordination is presented. The approach depends on the apparent impedance loci seen by the distance relay during all possible disturbances. In a distance relay, the impedance loci seen at the relay location is obtained by extensive transient stability studies. Support vector machines (SVMs), a class of patterns classifiers are used in discriminating zone settings (zone-1, zone-2 and zone-3) using the signals to be used by the relay. Studies on a sample 9-bus are presented for illustrating the proposed scheme.

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The decentralized power is characterised by generation of power nearer to the demand centers, focusing mainly on meeting local energy needs. A decentralized power system can function either in the presence of grid, where it can feed the surplus power generated to the grid, or as an independent/stand-alone isolated system exclusively meeting the local demands of remote locations. Further, decentralized power is also classified on the basis of type of energy resources used-non-renewable and renewable. These classifications along with a plethora of technological alternatives have made the whole prioritization process of decentralized power quite complicated for decision making. There is abundant literature, which has discussed various approaches that have been used to support decision making under such complex situations. We envisage that summarizing such literature and coming out with a review paper would greatly help the policy/decision makers and researchers in arriving at effective solutions. With such a felt need 102 articles were reviewed and features of several technological alternatives available for decentralized power, the studies on modeling and analysis of economic, environmental and technological asibilities of both grid-connected (GC) and stand-alone (SA) systems as decentralized power options are presented. (C) 2009 Elsevier Ltd. All rights reserved.

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A simple ramp control firing circuit, suitable for use with fully controlled, line-commutated thyristor bridge circuits, is discussed here. This circuit uses very few components and generates the synchronized firing pulses in a simple way. It operates from a single 15 V Supply and has an inherent pulse inhibit facility. This circuit provides the synchronized firing pulses for both thyristors of the same limb in a bridge. To ensure reliability, wide triggering pulses are used, which are modulated to pass through the pulse transformers1 and demodulated before being fed to the thyristor gates. The use of throe such circuits only for a three-phase bridge is discussed.

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The self-triggering action of the TVG under DC conditions using the same power source as the main circuit is described. Because of the low impedance of the power source compared with the thyratron pulse generator, the TVG can be triggered with voltages as low as 85 V. It is found that circuit conditions influence the minimum stable arc currents that can be sustained.

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The recently developed single network adaptive critic (SNAC) design has been used in this study to design a power system stabiliser (PSS) for enhancing the small-signal stability of power systems over a wide range of operating conditions. PSS design is formulated as a discrete non-linear quadratic regulator problem. SNAC is then used to solve the resulting discrete-time optimal control problem. SNAC uses only a single critic neural network instead of the action-critic dual network architecture of typical adaptive critic designs. SNAC eliminates the iterative training loops between the action and critic networks and greatly simplifies the training procedure. The performance of the proposed PSS has been tested on a single machine infinite bus test system for various system and loading conditions. The proposed stabiliser, which is relatively easier to synthesise, consistently outperformed stabilisers based on conventional lead-lag and linear quadratic regulator designs.

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The Printed Circuit Board (PCB) layout design is one of the most important and time consuming phases during equipment design process in all electronic industries. This paper is concerned with the development and implementation of a computer aided PCB design package. A set of programs which operate on a description of the circuit supplied by the user in the form of a data file and subsequently design the layout of a double-sided PCB has been developed. The algorithms used for the design of the PCB optimise the board area and the length of copper tracks used for the interconnections. The output of the package is the layout drawing of the PCB, drawn on a CALCOMP hard copy plotter and a Tektronix 4012 storage graphics display terminal. The routing density (the board area required for one component) achieved by this package is typically 0.8 sq. inch per IC. The package is implemented on a DEC 1090 system in Pascal and FORTRAN and SIGN(1) graphics package is used for display generation.