A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

A Neuro-Adaptive Approach for Robust Control of High Performance Aircrafts with Parameter Inaccuracies

For high performance aircrafts, the flight control system needs to be quite effective in both assuring accurate tracking of pilot commands, while simultaneously assuring overall stability of the aircraft. In addition, the control system must also be sufficiently robust to cater to possible parameter variations. The primary aim of this paper is to enhance the robustness of the controller for a HPA using neuro-adaptive control design. Here the architecture employs a network of Gaussian Radial basis functions to adaptively compensate for the ignored system dynamics. A stable weight mechanism is determined using Lyapunov theory. The network construction and performance of the resulting controller are illustrated through simulations with a low-fidelity six –DOF model of F16 that is available in open literature.

Continuous-time Single Network Adaptive Critic for Regulator Design of Nonlinear Control Affine Systems

An optimal control law for a general nonlinear system can be obtained by solving Hamilton-Jacobi-Bellman equation. However, it is difficult to obtain an analytical solution of this equation even for a moderately complex system. In this paper, we propose a continuoustime single network adaptive critic scheme for nonlinear control affine systems where the optimal cost-to-go function is approximated using a parametric positive semi-definite function. Unlike earlier approaches, a continuous-time weight update law is derived from the HJB equation. The stability of the system is analysed during the evolution of weights using Lyapunov theory. The effectiveness of the scheme is demonstrated through simulation examples.

Streaming FFT on REDEFINE-v2: An Application-Architecture Design Space Exploration

In this paper we explore an implementation of a high-throughput, streaming application on REDEFINE-v2, which is an enhancement of REDEFINE. REDEFINE is a polymorphic ASIC combining the flexibility of a programmable solution with the execution speed of an ASIC. In REDEFINE Compute Elements are arranged in an 8x8 grid connected via a Network on Chip (NoC) called RECONNECT, to realize the various macrofunctional blocks of an equivalent ASIC. For a 1024-FFT we carry out an application-architecture design space exploration by examining the various characterizations of Compute Elements in terms of the size of the instruction store. We further study the impact by using application specific, vectorized FUs. By setting up different partitions of the FFT algorithm for persistent execution on REDEFINE-v2, we derive the benefits of setting up pipelined execution for higher performance. The impact of the REDEFINE-v2 micro-architecture for any arbitrary N-point FFT (N > 4096) FFT is also analyzed. We report the various algorithm-architecture tradeoffs in terms of area and execution speed with that of an ASIC implementation. In addition we compare the performance gain with respect to a GPP.

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip

Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and lower energy consumption. The memory architecture of the embedded system strongly influences these parameters. Hence the embedded system designer performs a complete memory architecture exploration. This problem is a multi-objective optimization problem and can be tackled as a two-level optimization problem. The outer level explores various memory architecture while the inner level explores placement of data sections (data layout problem) to minimize memory stalls. Further, the designer would be interested in multiple optimal design points to address various market segments. However, tight time-to-market constraints enforces short design cycle time. In this paper we address the multi-level multi-objective memory architecture exploration problem through a combination of Multi-objective Genetic Algorithm (Memory Architecture exploration) and an efficient heuristic data placement algorithm. At the outer level the memory architecture exploration is done by picking memory modules directly from a ASIC memory Library. This helps in performing the memory architecture exploration in a integrated framework, where the memory allocation, memory exploration and data layout works in a tightly coupled way to yield optimal design points with respect to area, power and performance. We experimented our approach for 3 embedded applications and our approach explores several thousand memory architecture for each application, yielding a few hundred optimal design points in a few hours of computation time on a standard desktop.

Command Tracking in High Performance Aircrafts: A New Dynamic Inversion Design

This paper proposes a new straight forward technique based on dynamic inversion, which is applied for tracking the pilot commands in high performance aircrafts.Pilot commands assumed in longitudinal mode are normal acceleration and total velocity(while roll angle and lateral acceleration are maintained at zero). In lateral mode, roll rate and total velocity are used as pilot commands (while climb rate and lateral acceleration are maintained at zero). Ensuring zero lateral acceleration leads to a better turn co-ordination. A six degree-of-freedom model of F-16 aircraft is used for both control design as well as simulation studies. Promising results are obtained which are found to be superior as compared to an existing approach (which is also based on dynamic inversion). The new approach has two potential benefits, namely reduced oscillatory response and reduced control magnitude. Another advantage of this approach is that it leads to a significant reduction of tuning parameters in the control design process.

Model-following Neuro-adaptive approach for robust control of high performance aircrafts

Based on dynamic inversion, a relatively straightforward approach is presented in this paper for nonlinear flight control design of high performance aircrafts, which does not require the normal and lateral acceleration commands to be first transferred to body rates before computing the required control inputs. This leads to substantial improvement of the tracking response. Promising results are obtained from six degree-offreedom simulation studies of F-16 aircraft, which are found to be superior as compared to an existing approach (which is also based on dynamic inversion). The new approach has two potential benefits, namely reduced oscillatory response (including elimination of non-minimum phase behavior) and reduced control magnitude. Next, a model-following neuron-adaptive design is augmented the nominal design in order to assure robust performance in the presence of parameter inaccuracies in the model. Note that in the approach the model update takes place adaptively online and hence it is philosophically similar to indirect adaptive control. However, unlike a typical indirect adaptive control approach, there is no need to update the individual parameters explicitly. Instead the inaccuracy in the system output dynamics is captured directly and then used in modifying the control. This leads to faster adaptation, which helps in stabilizing the unstable plant quicker. The robustness study from a large number of simulations shows that the adaptive design has good amount of robustness with respect to the expected parameter inaccuracies in the model.

Recent Advances in Low CTE and High Density System-on-a-Package (SOP) Substrate with Thin Film Component Integration

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, optical, and sensor functions integrated in a single package/module. The goal of this effort is to develop a platform substrate technology providing very high wiring density and embedded thin film passive and active components using PWB compatible materials and processes. The latest SOP baseline process test vehicle has been fabricated on novel Si-matched CTE, high modulus C-SiC composite core substrates using 10mum thick BCB dielectric films with loss tangent of 0.0008 and dielectric constant of 2.65. A semi-additive plating process has been developed for multilayer microvia build-up using BCB without the use of any vacuum deposition or polishing/CMP processes. PWB and package substrate compatible processes such as plasma surface treatment/desmear and electroless/electrolytic pulse reverse plating was used. The smallest line width and space demonstrated in this paper is 6mum with microvia diameters in the 15-30mum range. This build-up process has also been developed on medium CTE organic laminates including MCL-E-679F from Hitachi Chemical and PTFE laminates with Cu-Invar-Cu core. Embedded decoupling capacitors with capacitance density of >500nF/cm2 have been integrated into the build-up layers using sol-gel synthesized BaTiO3 thin films (200-300nm film thickness) deposited on copper foils and integrated using vacuum lamination and subtractive etch processes. Thin metal alloy resistor films have been integrated into the SOP substrate using two methods: (a) NiCrAlSi thin films (25ohms per square) deposited on copper foils (Gould Electronics) laminated on the build-up layers and two step etch process for resistor definition, and (b) electroless plated Ni-W-P thin films (70 ohms to few Kohms per square) on the BCB dielectric by plasma surface treatment and activation. The electrical design and build-up layer structure along- - with key materials and processes used in the fabrication of the SOP4 test vehicle were presented in this paper. Initial results from the high density wiring and embedded thin film components were also presented. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation