Integrated higher-order pulse-width modulation filter-transformer structure for single-phase static compensator

A power filter is necessary to connect the output of a power converter to the grid so as to reduce the harmonic distortion introduced in the line current and voltage by the power converter. Many a times, a transformer is also present before the point of common coupling. Magnetic components often constitute a significant part of the overall weight, size and cost of the grid interface scheme. So, a compact inexpensive design is desirable. A higher-order LCL-filter and a transformer are increasingly being considered for grid interconnection of the power converter. This study proposes a design method based on a three-winding transformer, that generates an integrated structure that behaves as an LCL-filter, with both the filter inductances and the transformer that are merged into a single electromagnetic component. The parameters of the transformer are derived analytically. It is shown that along with a filter capacitor, the transformer parameters provide the filtering action of an LCL-filter. A single-phase full-bridge power converter is operated as a static compensator for performance evaluation of the integrated filter transformer. A resonant integrator-based single-phase phase locked loop and stationary frame AC current controller are employed for grid frequency synchronisation and line current control, respectively.

Graphene based E. coli sensor on flexible acetate sheet

A low cost, reagent free, Escherichia coli sensor is demonstrated with graphene, on transparent flexible acetate substrate. Graphene is grown on 100 mu m thick Cu foil, using CVD process and subsequently transferred on to a flexible acetate substrate. Gold electrodes are deposited on graphene to form a two terminal, interdigitated capacitor structure. Impedance spectroscopy (10 Hz to 100 kHz) is performed to characterize the change in impedance, as a function of E. coli concentration on graphene surface. The residual methyl groups on graphene, resulting from the transfer process, act as binding sites for E. coli. It has been observed that the resistance of graphene decreases with increasing E. coli concentration. This is due to the increased hole doping induced by negatively charged E. coli. A sensitivity of 60% is achieved for an E. coli concentration of 4.5 x 10(7) cfu/ml. An equivalent RC model is proposed to explain the sensing mechanism. (C) 2013 Elsevier B.V. All rights reserved.

Variable field ion traps

This paper presents a technique to vary the electric field within a cylindrical ion trap (CIT) mass spectrometer while it is in operation. In this technique, the electrodes of the CIT are split into number of mini-electrodes and different voltages are applied to these split-electrodes to achieve the desired field. In our study we have investigated two geometries of the split-electrode CIT. In the first, we retain the flat endcap electrodes of the CIT but split the ring electrode into five mini-rings. In the second configuration, we split the ring electrode of the CIT into three mini-rings and also divide the endcaps into two mini-discs. By applying different potentials to the mini-rings and mini-discs of these geometries we have shown that the field within the trap can be optimized to desired values. In our study, two different types of fields were targeted. In the first, potentials were adjusted to obtain a linear electric field and, in the second, a controlled higher order even multipole field was obtained by adjusting the potential. We have shown that the different potentials required can be derived from a single RF generator by connecting appropriate capacitor terminations to split electrodes. The field within the trap can be modified by changing the values of the external capacitors. (C) 2013 Elsevier B.V. All rights reserved.

A Reduced Device-Count Hybrid Multilevel Inverter Topology with single DC Source and Improved Fault Tolerance

A new hybrid multilevel power converter topology is presented in this paper. The proposed power converter topology uses only one DC source and floating capacitors charged to asymmetrical voltage levels, are used for generating different voltage levels. The SVPWM based control strategy used in this converter maintains the capacitor voltages at the required levels in the entire modulation range including the over-modulation region. For the voltage levels: nine and above, the number of components required in the proposed topology is significantly lower, compared to the conventional multilevel inverter topologies. The number of capacitors required in this topology reduces drastically compared to the conventional flying capacitor topology, when the number of levels in the inverter output increases. This topology has better fault tolerance, as it is capable of operating with reduced number of levels, in the entire modulation range, in the event of any failure in the H-bridges. The transient as well as the steady state performance of the nine-level version of the proposed topology is experimentally verified in the entire modulation range including the over-modulation region.

A Seventeen-level Inverter With a Single DC-link For Motor Drives

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

A Harmonic Suppression Scheme for Open-End Winding Split-Phase IM Drive Using Capacitive Filters for the Full Speed Range

Voltage source inverter (VSI)-fed six-phase induction motor (IM) drives have high 6n +/- 1, n = odd-order harmonic currents. This is because these currents, driven by the corresponding harmonic voltages in the inverter output, are limited only by the stator leakage impedance, as these harmonics are absent in the back electromotive force of the motor. To suppress the harmonic currents, either bulky inductive harmonic filters or complex pulsewidth modulation (PWM) techniques have to be used. This paper proposes a harmonic elimination scheme using switched capacitor filters for a VSI-fed split-phase IM drive. Two 3-phase inverters fed from capacitors are used on the open-end side of the motor to suppress 6n +/- 1, n = odd-order harmonics. A PWM scheme that can suppress the harmonics as well as balance the capacitor voltage is also proposed. The capacitor fed inverters are switched so that the fundamental voltage is not affected, and the fundamental power is always drawn from the main inverters. The proposed scheme is verified with a detailed experimental study. The effectiveness of the scheme is demonstrated by comparing the results with those obtained by disabling the capacitor fed inverters.

Influence of O-2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O-2 flow rate, during vaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O-2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O-2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O-2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O-2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices.

Coconut kernel-derived activated carbon as electrode material for electrical double-layer capacitors

Carbonization of milk-free coconut kernel pulp is carried out at low temperatures. The carbon samples are activated using KOH, and electrical double-layer capacitor (EDLC) properties are studied. Among the several samples prepared, activated carbon prepared at 600 A degrees C has a large surface area (1,200 m(2) g(-1)). There is a decrease in surface area with increasing temperature of preparation. Cyclic voltammetry and galvanostatic charge-discharge studies suggest that activated carbons derived from coconut kernel pulp are appropriate materials for EDLC studies in acidic, alkaline, and non-aqueous electrolytes. Specific capacitance of 173 F g(-1) is obtained in 1 M H2SO4 electrolyte for the activated carbon prepared at 600 A degrees C. The supercapacitor properties of activated carbon sample prepared at 600 A degrees C are superior to the samples prepared at higher temperatures.

Medium-Voltage Drive for Induction Machine With Multilevel Dodecagonal Voltage Space Vectors With Symmetric Triangles

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept.

A 5th and 7th order harmonic suppression scheme using capacitive filtering for 2-level VSI fed IM drive

In this paper, a 5th and 7th harmonic suppression technique for a 2-level VSI fed IM drive, by using capacitive filtering is proposed. A capacitor fed 2-level inverter is used on an open-end winding induction motor to suppress all 5th and 7th order harmonics. A PWM scheme that maintains the capacitor voltage, while suppressing the harmonics is also proposed. The proposed scheme is valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

Sensing of Stimulus Artifact Suppressed Signals From Electrode Interfaces

Stimulus artifacts inhibit reliable acquisition of biological evoked potentials for several milliseconds if an electrode contact is utilized for both electrical stimulation and recording purposes. This hinders the measurement of evoked short-latency biological responses, which is otherwise elicited by stimulation in implantable prosthetic devices. We present an improved stimulus artifact suppression scheme using two electrode simultaneous stimulation and differential readout using high-gain amplifiers. Substantial reduction of artifact duration has been shown possible through the common-mode rejection property of an instrumentation amplifier for electrode interfaces. The performance of this method depends on good matching of electrode-electrolyte interface properties of the chosen electrode pair. A novel calibration algorithm has been developed that helps in artificial matching of impedance and thereby achieves the required performance in artifact suppression. Stimulus artifact duration has been reduced down to 50 mu s from the stimulation-cum-recording electrodes, which is similar to 6x improvement over the present state of the art. The system is characterized with emulated resistor-capacitor loads and a variety of in-vitro metal electrodes dipped in saline environment. The proposed method is going to be useful for closed-loop electrical stimulation and recording studies, such as bidirectional neural prosthesis of retina, cochlea, brain, and spinal cord.

Low-Order Harmonic Suppression for Open-End Winding IM With Dodecagonal Space Vector Using a Single DC-Link Supply

This paper proposes a technique to suppress low-order harmonics for an open-end winding induction motor drive for a full modulation range. One side of the machine is connected to a main inverter with a dc power supply, whereas the other inverter is connected to a capacitor from the other side. Harmonic suppression (with complete elimination of fifth- and seventh-order harmonics) is achieved by realizing dodecagonal space vectors using a combined pulsewidth modulation (PWM) control for the two inverters. The floating capacitor voltage is inherently controlled during the PWM operation. The proposed PWM technique is shown to be valid for the entire modulation range, including overmodulation and six-step mode of operation of the main inverter. Experimental results have been presented to validate the proposed technique.

Active Power Decoupling with Reduced Converter Stress for Single-Phase Power Conversion and Interfacing

Single-phase DC/AC power electronic converters suffer from pulsating power at double the line frequency. The commonest practice to handle the issue is to provide a huge electrolytic capacitor for smoothening out the ripple. But, the electrolytic capacitors having short end of lifetimes limit the overall lifetime of the converter. Another way of handling the ripple power is by active power decoupling (APD) using the storage devices and a set of semiconductor switches. Here, a novel topology has been proposed implementing APD. The topology claims the benefit of 1) reduced stress on converter switches 2) using smaller capacitance value thus alleviating use of electrolytic capacitor in turn improving the lifetime of the converter. The circuit consists of a third leg, a storage capacitor and a storage inductor. The analysis and the simulation results are shown to prove the effectiveness of the topology.

Active Power Decoupling with Reduced Converter Stress for Single-Phase Power Conversion and Interfacing

Single-phase DC/AC power electronic converters suffer from pulsating power at double the line frequency. The commonest practice to handle the issue is to provide a huge electrolytic capacitor for smoothening out the ripple. But, the electrolytic capacitors having short end of lifetimes limit the overall lifetime of the converter. Another way of handling the ripple power is by active power decoupling (APD) using the storage devices and a set of semiconductor switches. Here, a novel topology has been proposed implementing APD. The topology claims the benefit of 1) reduced stress on converter switches 2) using smaller capacitance value thus alleviating use of electrolytic capacitor in turn improving the lifetime of the converter. The circuit consists of a third leg, a storage capacitor and a storage inductor. The analysis and the simulation results are shown to prove the effectiveness of the topology.