Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

A Fast Linear Separability Test by Projection of Positive Points on Subspaces

A geometric and non parametric procedure for testing if two finite set of points are linearly separable is proposed. The Linear Separability Test is equivalent to a test that determines if a strictly positive point h > 0 exists in the range of a matrix A (related to the points in the two finite sets). The algorithm proposed in the paper iteratively checks if a strictly positive point exists in a subspace by projecting a strictly positive vector with equal co-ordinates (p), on the subspace. At the end of each iteration, the subspace is reduced to a lower dimensional subspace. The test is completed within r ≤ min(n, d + 1) steps, for both linearly separable and non separable problems (r is the rank of A, n is the number of points and d is the dimension of the space containing the points). The worst case time complexity of the algorithm is O(nr3) and space complexity of the algorithm is O(nd). A small review of some of the prominent algorithms and their time complexities is included. The worst case computational complexity of our algorithm is lower than the worst case computational complexity of Simplex, Perceptron, Support Vector Machine and Convex Hull Algorithms, if d

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

A Profilometric Approach to 3D Face Reconstruction and Its Application to Face Recognition

3D Face Recognition is an active area of research for past several years. For a 3D face recognition system one would like to have an accurate as well as low cost setup for constructing 3D face model. In this paper, we use Profilometry approach to obtain a 3D face model.This method gives a low cost solution to the problem of acquiring 3D data and the 3D face models generated by this method are sufficiently accurate. We also develop an algorithm that can use the 3D face model generated by the above method for the recognition purpose.

0.84 ps Resolution Clock Skew Measurement via Subsampling

An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are sub-sampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of +/- 1 fan-out-of-4 (FO4) delay, +/- 3 sigma resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks.

Creep behaviour of short fibre reinforced QE22 magnesium alloy using impression creep test

Creep properties of QE22 magnesium based alloy and composites reinforced with 20 volume percent of short-fibers - Maftech (R), Saffil (R) or Supertech (R), were evaluated using the impression creep test. In the impression creep test, a load is applied with the help of a cylindrical tungsten carbide indenter of 1 mm diameter. This has advantages over conventional creep testing in terms of small specimen size requirement and simple machining. Depth of impression is recorded with time and steady state strain rate is obtained from the slope of the secondary strain (depth of impression divided by indenter diameter) vs. time plot. The results are compared with the creep obtained from conventional creep performed in tension on the same materials earlier. Microstructural examination of the plastically deformed regions is carried out to explain creep behaviour of these composites.

Prediction of extension test results of soft cemented clays with a simple constitutive model

In the present paper, the constitutive model is proposed for cemented soils, in which the cementation component and frictional component are treated separately and then added together to get overall response. The modified Cam clay is used to predict the frictional resistance and an elasto-plastic strain softening model is proposed for the cementation component. The rectangular isotropic yield curve proposed by Vatsala (1995) for the bond component has been modified in order to account for the anisotropy generally observed in the case of natural soft cemented soils. In this paper, the model proposed is used to predict the experimental results of extension tests on the soft cemented soils whereas compression test results are presented elsewhere. The model predictions compare quite satisfactorily with the observed response. A few input parameters are required which are well defined and easily determinable and the model uses associated flow rule.

Does acoustic adaptation drive vertical stratification? A test in a tropical cricket assemblage

In species-rich assemblages, differential utilization of vertical space can be driven by resource availability. For animals that communicate acoustically over long distances under habitat-induced constraints, access to an effective transmission channel is a valuable resource. The acoustic adaptation hypothesis suggests that habitat acoustics imposes a selective pressure that drives the evolution of both signal structure and choice of calling sites by signalers. This predicts that species-specific signals transmit best in native habitats. In this study, we have tested the hypothesis that vertical stratification of calling heights of acoustically communicating species is driven by acoustic adaptation. This was tested in an assemblage of 12 coexisting species of crickets and katydids in a tropical wet evergreen forest. We carried out transmission experiments using natural calls at different heights from the forest floor to the canopy. We measured signal degradation using 3 different measures: total attenuation, signal-to-noise ratio (SNR), and envelope distortion. Different sets of species supported the hypothesis depending on which attribute of signal degradation was examined. The hypothesis was upheld by 5 species for attenuation and by 3 species each for SNR and envelope distortion. Only 1 species of 12 provided support for the hypothesis by all 3 measures of signal degradation. The results thus provided no overall support for acoustic adaptation as a driver of vertical stratification of coexisting cricket and katydid species.

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy-performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy-delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure. (C) 2012 Elsevier Inc. All rights reserved.

A weighted average-based external clock synchronisation protocol for wireless sensor networks

Wireless Sensor Networks (WSNs) have many application scenarios where external clock synchronisation may be required because a WSN may consist of components which are not connected to each other. In this paper, we first propose a novel weighted average-based internal clock synchronisation (WICS) protocol, which synchronises all the clocks of a WSN with the clock of a reference node periodically. Based on this protocol, we then propose our weighted average-based external clock synchronisation (WECS) protocol. We have analysed the proposed protocols for maximum synchronisation error and shown that it is always upper bounded. Extensive simulation studies of the proposed protocols have been carried out using Castalia simulator. Simulation results validate our above theoretical claim and also show that the proposed protocols perform better in comparison to other protocols in terms of synchronisation accuracy. A prototype implementation of the WICS protocol using a few TelosB motes also validates the above conclusions.

Functional maps within a single neuron

Narayanan R, Johnston D. Functional maps within a single neuron. J Neurophysiol 108: 2343-2351, 2012. First published August 29, 2012; doi:10.1152/jn.00530.2012.-The presence and plasticity of dendritic ion channels are well established. However, the literature is divided on what specific roles these dendritic ion channels play in neuronal information processing, and there is no consensus on why neuronal dendrites should express diverse ion channels with different expression profiles. In this review, we present a case for viewing dendritic information processing through the lens of the sensory map literature, where functional gradients within neurons are considered as maps on the neuronal topograph. Under such a framework, drawing analogies from the sensory map literature, we postulate that the formation of intraneuronal functional maps is driven by the twin objectives of efficiently encoding inputs that impinge along different dendritic locations and of retaining homeostasis in the face of changes that are required in the coding process. In arriving at this postulate, we relate intraneuronal map physiology to the vast literature on sensory maps and argue that such a metaphorical association provides a fresh conceptual framework for analyzing and understanding single-neuron information encoding. We also describe instances where the metaphor presents specific directions for research on intraneuronal maps, derived from analogous pursuits in the sensory map literature. We suggest that this perspective offers a thesis for why neurons should express and alter ion channels in their dendrites and provides a framework under which active dendrites could be related to neural coding, learning theory, and homeostasis.

Design and analysis of a peer-to-peer based distributed clock synchronisation protocol for wireless sensor networks

Clock synchronisation is an important requirement for various applications in wireless sensor networks (WSNs). Most of the existing clock synchronisation protocols for WSNs use some hierarchical structure that introduces an extra overhead due to the dynamic nature of WSNs. Besides, it is difficult to integrate these clock synchronisation protocols with sleep scheduling scheme, which is a major technique to conserve energy. In this paper, we propose a fully distributed peer-to-peer based clock synchronisation protocol, named Distributed Clock Synchronisation Protocol (DCSP), using a novel technique of pullback for complete sensor networks. The pullback technique ensures that synchronisation phases of any pair of clocks always overlap. We have derived an exact expression for a bound on maximum synchronisation error in the DCSP protocol, and simulation study verifies that it is indeed less than the computed upper bound. Experimental study using a few TelosB motes also verifies that the pullback occurs as predicted.